Abstract: A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

Abstract: A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

Abstract: A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.

Abstract: An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Three representative embodiments of the key structure are described in detail.

Abstract: A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

Abstract: A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

Abstract: A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.

Abstract: Junction field-effect transistors (JFETs) having insulator-isolated source/drain regions and fabrication methods therefor are disclosed here. In SOI JFETs and bulk silicon JFETs having junction isolated source and drain regions from the body region, the junction leakage current is one of the leakage components of the off-state leakage current and consequently limits the on-off switching performance. In particular, for short-channel devices (for example, sub-100 nm and/or sub-65 nm devices), the leakage currents are especially pronounced. The techniques herein introduced include JFET with an insulating spacer such that the source and drain regions are insulator isolated from the body region. In one embodiment, the source and drain regions of the transistor are insulator isolated by silicon dioxide thus reducing the source-drain to body junction leakage current and improved on-off performance.

Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

Abstract: A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region.

Abstract: A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

Abstract: A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.