Patents by Inventor Ashok Vittal
Ashok Vittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7728623Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.Type: GrantFiled: October 9, 2006Date of Patent: June 1, 2010Assignee: Agate Logic, Inc.Inventors: Hare K. Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
-
Patent number: 7605605Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.Type: GrantFiled: January 27, 2005Date of Patent: October 20, 2009Assignee: Cswitch CorporationInventors: Hare K. Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
-
Patent number: 7417455Abstract: A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.Type: GrantFiled: May 14, 2005Date of Patent: August 26, 2008Assignee: CSwitch CorporationInventors: Hare K. Verma, Ashok Vittal
-
Publication number: 20070085564Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.Type: ApplicationFiled: October 9, 2006Publication date: April 19, 2007Applicant: Velogix, Inc.Inventors: Hare Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
-
Publication number: 20060164120Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.Type: ApplicationFiled: January 27, 2005Publication date: July 27, 2006Applicant: Flexlogics, Inc.Inventors: Hare Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
-
Patent number: 6980029Abstract: A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic modules. The first level is fed from a bank of memory elements and the inputs to this bank of memory elements are derived from the last level. Crossbar switches are optionally inserted between a carefully chosen pairs of levels.Type: GrantFiled: December 13, 2002Date of Patent: December 27, 2005Assignee: Velogix, Inc.Inventors: Ashok Vittal, Hare K. Verma
-
Programmable function generator and method operating as combinational, sequential, and routing cells
Patent number: 6980025Abstract: A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.Type: GrantFiled: September 2, 2003Date of Patent: December 27, 2005Assignee: Velogix, Inc.Inventors: Hare Krishna Verma, Ashok Vittal -
Publication number: 20050206406Abstract: A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.Type: ApplicationFiled: May 14, 2005Publication date: September 22, 2005Applicant: Velogix, Inc.Inventors: Hare Verma, Ashok Vittal
-
Patent number: 6349403Abstract: An efficient, gridless, cost-based coarse router having layer assignment for a computer controlled integrated circuit design. The coarse routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the coarse wire routing process, a number of obstructions are defined. Next, the horizontal and vertical passages between adjacent obstructions, through which wires may be routed, are determined. The costs for possible wire paths connecting a pair of pins are computed based upon wire density histograms associated with the various passages through which the paths traverse. The lowest cost path is then selected. In order to increase the processing speed, a pruning method is employed to minimize the number of possible paths to be considered. In some instances, there may be areas which are overly congested. For overly congested areas, a pseudo obstruction is artificially created by the coarse router.Type: GrantFiled: December 18, 1998Date of Patent: February 19, 2002Assignee: Synopsys, Inc.Inventors: Shiraj Robi Dutta, Pravin K. Madhani, Ashok Vittal, Nagaraja Ravindranath Rao
-
Patent number: 6324675Abstract: An efficient iterative, gridless, cost-based router for a computer controlled integrated circuit design. The fine routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the wire routing process, wires are routed between pins of nets. The routing process of the present invention is gridless and utilizes lanes that are defined based on the boundaries of objects. The cost-based router computes a cost for each wire path, and the cost is based on: (1) the manhattan wire distance: (2) the layers in which the wire runs; and (3) any overlap the wire has with soft obstacles (e.g., other wires, etc.); and (4) an estimated cost to the target. Cost computation is reduced by considering only obstacles within the layer in which a lane is run. The number of paths determined for a wire route is reduced by pruning possible paths based on the placement of obstacles within the integrated circuit.Type: GrantFiled: December 18, 1998Date of Patent: November 27, 2001Assignee: Synopsys, Inc.Inventors: Robi Dutta, Ravi Rao, Ashok Vittal
-
Patent number: 6223334Abstract: The present invention includes a net topology strategy, referred to as a J-tree model, that meets monotonicity and ring back constraints for nets with bi-directional drivers without much degradation in delay. The present invention includes a method that can be used to automatically construct a J-tree for a given net. A J-tree is generated by identifying at least two clusters of nodes and interconnecting the nodes so that each node has a sibling node that is the same distance from a parent node. Each cluster comprises at least a minimum geometric number of nodes. The nodes are interconnected by first locating a star point for each cluster so that the nodes in each cluster are equidistant from the star point. Then, the star point for each cluster is interconnected forming the topology.Type: GrantFiled: October 1, 1998Date of Patent: April 24, 2001Assignee: Mentor Graphics CorporationInventors: Peter R. Suaris, Ashok Vittal