Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more operations in a sequence of operations to be performed by one or more accelerators within a heterogeneous processor.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more memory regions to store error information from one or more accelerators within a heterogeneous processor.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to transfer information between memory of two or more accelerators.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media that generate a digital document hierarchy comprising layers of parent-child element relationships from the visual elements. For example, for a layer of the layers, the disclosed systems determine, from the visual elements, candidate parent visual elements and child visual elements. In addition, for the layer of the layers, the disclosed systems generate, from the feature embeddings utilizing a neural network, element classifications for the candidate parent visual elements and parent-child element link probabilities for the candidate parent visual elements and the child visual elements. Moreover, for the layer, the disclosed systems select parent visual elements from the candidate parent visual elements based on the parent-child element link probabilities. Further, the disclosed systems utilize the digital document hierarchy to generate an interactive digital document from the digital document image.

Abstract: An example medical device includes a device housing configured to be implantable within a patient, the device housing including an internal surface in contact with a voltaic cell of the battery, and a battery external to the device housing and comprising a battery housing configured to be hermetically sealed. The battery is configured to provide electrical power to an electrical component housed within the device housing, and the battery housing is configured to be attached to the device housing. The battery housing includes an internal surface in contact with a voltaic cell of the battery, and an external surface in contact with the biocompatible electrical insulator. an external surface in contact with the biocompatible electrical insulator.

Abstract: Systems and methods for training an object detection network are described. Embodiments train an object detection network using a labeled training set, wherein each element of the labeled training set includes an image and ground truth labels for object instances in the image, predict annotation data for a candidate set of unlabeled data using the object detection network, select a sample image from the candidate set using a policy network, generate a labeled sample based on the selected sample image and the annotation data, wherein the labeled sample includes labels for a plurality of object instances in the sample image, and perform additional training on the object detection network based at least in part on the labeled sample.

Abstract: In various examples, techniques for performing software code verification are described. Systems and methods are disclosed for generating, using intermediate code and user input, a call graph that represents source code for software. For instance, the call graph represents at least functions (e.g., internal functions, external functions, etc.) associated with the software, calls (e.g., direct calls, call pointers, etc.) between the functions, and register information associated with the functions (e.g., variables used by the functions, assembly code used by the functions, etc.). The systems and methods may further use the call graph to perform software code verification by verifying rules from design specifications for the software and/or rules from various certification standards.

Abstract: Apparatuses, systems, and techniques to indicate contextual information to be used by available logical processors. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate a first set of contextual information to be used by a first subset of available processors.

Abstract: A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Abstract: In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Abstract: A computer-implemented method for characterizing a crowd that includes recording a video stream of individuals at a location having at least one reference point for viewing; and extracting the individuals from frames of the video streams. The method may further include assigning tracking identification values to the individuals that have been extracted from the video streams; and measuring at least one type classification from the individuals having the tracking identification values. The method may further include generating a crowd designation further characterizing the individuals having the tracking identification values in the location, the crowd designation comprising at least one measurement of probability that the individuals having the tracking identification values in the location view the at least one reference point for viewing.

Abstract: A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.