Patents by Inventor Ashutosh Malshe

Ashutosh Malshe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220392561
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.
    Type: Application
    Filed: August 16, 2022
    Publication date: December 8, 2022
    Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
  • Publication number: 20220391088
    Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11520699
    Abstract: A processing device of a memory sub-system is configured to receive a request to add content to a system data structure, wherein a first plurality of blocks of a common pool of blocks are allocated to the system data structure and a second plurality of blocks of the common pool of blocks are allocated to user data; determine whether user data has been written to the second plurality of blocks of the common pool of blocks within a threshold amount of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold amount of time, allocate a block from the second plurality of blocks of the common pool of blocks allocated to user data to the first plurality of blocks of the common pool of blocks allocated for the system data structure.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Kulachet Tanpairoj, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Patent number: 11521699
    Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
  • Publication number: 20220383962
    Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.
    Type: Application
    Filed: August 12, 2022
    Publication date: December 1, 2022
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Renato C. Padilla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
  • Patent number: 11507300
    Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Ashutosh Malshe, Gianni Stephen Alsasua, Renato Padilla, Jr., Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish Reddy Singidi
  • Patent number: 11494102
    Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20220350520
    Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, JR., Kishore K. Muchherla, Ashutosh Malshe, Niccolo' Righetti
  • Publication number: 20220343984
    Abstract: A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20220342813
    Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Inventors: Kishore Kumar Muchherla, Giuseppina Puzzilli, Vamsi Pavan Rayaprolu, Ashutosh Malshe, James Fitzpatrick, Shyam Sunder Raghunathan, Violante Moschiano, Tecla Ghilardi
  • Publication number: 20220334756
    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 20, 2022
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Giuseppina Puzzilli, Saeed Sharifi Tehrani
  • Publication number: 20220334751
    Abstract: Exemplary methods, apparatuses, and systems include receiving a plurality of read operations directed to a portion of memory accessed by a memory channel. The plurality of read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A supplemental memory location is selected independently of aggressors and victims in the current set of read operations. A first data integrity scan is performed on a victim of the aggressor read operation and a second data integrity scan is performed on the supplemental memory location.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Saeed Sharifi Tehrani, Ashutosh Malshe, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Vamsi Pavan Rayaprolu
  • Patent number: 11474738
    Abstract: Exemplary methods, apparatuses, and systems include receiving a plurality of read operations directed to a portion of memory accessed by a memory channel. The plurality of read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A supplemental memory location is selected independently of aggressors and victims in the current set of read operations. A first data integrity scan is performed on a victim of the aggressor read operation and a second data integrity scan is performed on the supplemental memory location.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: October 18, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Saeed Sharifi Tehrani, Ashutosh Malshe, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Vamsi Pavan Rayaprolu
  • Patent number: 11475974
    Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
  • Patent number: 11467980
    Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Publication number: 20220310183
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: Christopher M. Smitchger, Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Vamsi Pavan Rayaprolu, Ashutosh Malshe
  • Publication number: 20220310190
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
  • Patent number: 11456051
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
  • Patent number: 11456037
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Harish Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
  • Publication number: 20220300160
    Abstract: An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Xiangang Luo, Jianmin Huang, Ashutosh Malshe