Abstract: A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as Inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h1 and ?h1). A multiplexer can be placed at an input port of the second regeneration stage to select the set of speculative decision based on previous decision in order to save hardware and power. The DFE slicer samples the Input signal, regenerates the sampled data, stores the data on storage element like RS-latch or flip-flop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.

Abstract: A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h1 and ?h1). A multiplexer can be placed at an input port of the second regeneration stage to select the set of speculative decision based on previous decision in order to save hardware and power. The DFE slicer samples the input signal, regenerates the sampled data, stores the data on storage element like RS-latch or flip-flop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.