Abstract: An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in a design. Basically, the configurable design is an all-inclusive design having a large set of features, including varying interfaces, FIFO depths, and other features. Then, a derived design is generated by removing configurable constructs from the configurable design based on a specification, typically a customer specification received from a customer for a particular design. The specification indicates which configurable constructs are to be included in a derived design. Thereafter, the derived design is synthesizable in logic.

Abstract: An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in a design. Basically, the configurable design is an all-inclusive design having a large set of features, including varying interfaces, FIFO depths, and other features. Then, a derived design is generated by removing configurable constructs from the configurable design based on a specification, typically a customer specification received from a customer for a particular design. The specification indicates which configurable constructs are to be included in a derived design. Thereafter, the derived design is synthesizable in logic.

Abstract: A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.

Abstract: A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.