Patents by Inventor Ashwin Raghunathan
Ashwin Raghunathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8669794Abstract: A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.Type: GrantFiled: February 21, 2012Date of Patent: March 11, 2014Assignee: QUALCOMM IncorporatedInventors: Sang Wook Park, Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20130214831Abstract: A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.Type: ApplicationFiled: February 21, 2012Publication date: August 22, 2013Applicant: QUALCOMM IncorporatedInventors: Sang Wook Park, Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20130033331Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: QUALCOMM IncorporatedInventors: Ashwin RAGHUNATHAN, Marzio Pedrali-Noy, Sameer Wadhwa
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Patent number: 8362848Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.Type: GrantFiled: April 7, 2011Date of Patent: January 29, 2013Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy, Sameer Wadhwa
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Patent number: 8363485Abstract: A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).Type: GrantFiled: September 15, 2009Date of Patent: January 29, 2013Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali Noy
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Patent number: 8330511Abstract: A charge pump includes an UP current mirror and a DN current mirror. The UP current mirror is controlled by an input UP signal and supplies charge onto an output node. The DN current mirror is controlled by an input DN signal and draws charge from the output node. The input UP and DN signals may be received from a phase detector in a Phase-Locked Loop (PLL). To prevent disturbances on bias nodes of the UP and DN current mirrors that otherwise might occur, replica circuits of portions of the UP and DN current mirrors are provided. Each replica circuit is coupled to a bias node of a corresponding current mirror, but is controlled by an input signal of opposite polarity to the input signal that controls the current mirror so that the replica circuit creates disturbances that tend to counteract disturbances created by switching of the current mirror.Type: GrantFiled: April 20, 2010Date of Patent: December 11, 2012Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Sameer Wadhwa, Marzio Pedrali-Noy
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Publication number: 20120256693Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Applicant: QUALCOMM INCORPORATEDInventors: Ashwin Raghunathan, Marzio Pedrali-Noy, Sameer Wadhwa
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Patent number: 8164369Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.Type: GrantFiled: February 9, 2009Date of Patent: April 24, 2012Assignee: Qualcomm IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Patent number: 8159888Abstract: A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.Type: GrantFiled: March 1, 2010Date of Patent: April 17, 2012Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20110254615Abstract: A charge pump includes an UP current mirror and a DN current mirror. The UP current mirror is controlled by an input UP signal and supplies charge onto an output node. The DN current mirror is controlled by an input DN signal and draws charge from the output node. The input UP and DN signals may be received from a phase detector in a Phase-Locked Loop (PLL). To prevent disturbances on bias nodes of the UP and DN current mirrors that otherwise might occur, replica circuits of portions of the UP and DN current mirrors are provided. Each replica circuit is coupled to a bias node of a corresponding current mirror, but is controlled by an input signal of opposite polarity to the input signal that controls the current mirror so that the replica circuit creates disturbances that tend to counteract disturbances created by switching of the current mirror.Type: ApplicationFiled: April 20, 2010Publication date: October 20, 2011Applicant: QUALCOMM INCORPORATEDInventors: Ashwin Raghunathan, Sameer Wadhwa, Marzio Pedrali-Noy
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Publication number: 20110211404Abstract: A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.Type: ApplicationFiled: March 1, 2010Publication date: September 1, 2011Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Patent number: 7973612Abstract: A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.Type: GrantFiled: April 26, 2009Date of Patent: July 5, 2011Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Patent number: 7932757Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.Type: GrantFiled: February 9, 2009Date of Patent: April 26, 2011Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20110063929Abstract: A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali Noy
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Patent number: 7880554Abstract: A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted.Type: GrantFiled: April 29, 2009Date of Patent: February 1, 2011Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100271140Abstract: A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.Type: ApplicationFiled: April 26, 2009Publication date: October 28, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100194471Abstract: A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted.Type: ApplicationFiled: April 29, 2009Publication date: August 5, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100117701Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.Type: ApplicationFiled: February 9, 2009Publication date: May 13, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100117700Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.Type: ApplicationFiled: February 9, 2009Publication date: May 13, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy