Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.

Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.