Abstract: An image processor is divided into three sections for image acquisition and storage, image processing, and video output signal generation. The three sections are connected by an addrsss bus, a data bus and a set of control signal lines. A first bus control circuit is provided to isolate the image acquisition and storage section from the other sections during image acquisition and storage operations. A second bus control circuit isolates the video output section from the other sections, except during vertical and horizontal blanking intervals of the video output signal. The image is acquired by a line scan sensor which is clocked to acquire the image over one of several user definable exposure intervals. The video output presents the line scan sensor image in three formats. The first is a compressed representation of the entire line and the second is a less compressed representation of a selected portion of the image. The third display format is a binary version of the second image display format.