Abstract: A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions.

Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.

Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.

Abstract: A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators.

Abstract: The waveform of a strobe type signal (70) is specified by two bit strings (72, 74) stored in the RAM (20), one bit string (72) denoting when the strobe is to be reset and the other (74) denoting when the strobe is to be set. The bit positions in the bit strings correspond with clock cycles (76) taken for a DRAM memory access. The bit positions are written by means of addressable registers (71) corresponding to rows (e.g. 80-87) of the RAM. A one bit in the set bit string (72) causes the signal (70) to be asserted in the corresponding clock cycle of the request. A one bit in the reset bit string causes the signal (70) to be de-asserted in the corresponding clock cycle of the request. The set and reset times are fine-tuned to a fraction of a cycle by providing a multi-bit fractional cycle index field (78) to accompany each bit string. If a two bit quarter cycle index (QCI) field is used, the boundaries of the quarter cycles are numbered from 0 to 3.