Abstract: A reset signal generating circuit included in a phase comparator of a PLL circuit includes fourth and second transistors having their respective gates connected to the gates of first and third transistors in a crossed form. A reset signal is output through first and third transistors and through fourth and second transistors in response to output of signals UP and DOWN. Accordingly, the time period between the output of signals UP, DOWN, and the output of the reset signal is made constant regardless of which of the signals UP and DOWN has been output first.

Abstract: A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.

Abstract: An NMOS transistor (2) has a source electrode, a drain electrode and a gate electrode which are connected to a power source (VSS), an output terminal of a stepdown circuit (27), and a node (N2) between load elements (11, 12) respectively. The transistor size of the NMOS transistor (2) is so set that its drain current exerts no influence on fluctuation of an output voltage (VDD2) when an output voltage control operation by a differential amplification circuit (29) and the stepdown circuit (27) is functional to enable suppression of fluctuation of the output voltage (VDD2), while the output voltage (VDD2) is stepped down on the basis of the current quantity of the drain current of the NMOS transistor (2) when the output voltage control operation is unfunctional to disable suppression of fluctuation of the output voltage (VDD2). Thus, obtained is a voltage generation circuit which can reliably suppress fluctuation of the output voltage regardless of the frequency of fluctuation in source voltage.

Abstract: A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator. A phase comparator compares the phase of the output signal of the voltage control led oscillator with a reference signal. A loop filter to which the output signal of the comparator is applied provides a control signal to the voltage controlled oscillator. The voltage controlled oscillator is formed by interconnecting a plurality of oscillator components according to a desired wiring pattern. Each wiring pattern determines the basic oscillation frequency of the voltage controlled oscillator. A loop filter is formed by interconnecting a plurality of loop filter components according to another wiring pattern. Each wiring pattern determining the time constant of the loop filter. The oscillator components, the wiring pattern interconnectors, the comparator, the loop filter components and its wiring pattern interconnectors are disposed on a single substrate.

Abstract: A phase synchronization circuit including a phase-locked-loop synchronizes a phase of a clock signal with a phase of a reference clock signal having a frequency desired by a user. The gates of an NMOS transistor and a PMOS transistors are connected in common to a resistor. The drain and the source of the NMOS transistor are both connected to a ground potential while the drain and the source of the PMOS transistor are both connected to a power source voltage. By changing a number of NMOS and PMOS transistors formed during a metallization process, the capacitance in a loop filter is easily changed.

Abstract: A PLL circuit apparatus in accordance with the present invention includes a phase comparator, a delay circuit, a NOR circuit, and a loop filter. The phase comparator detects a phase difference between a reference clock signal and an internal clock signal. The delay circuit delays the reference clock signal by a delay time of an output of the phase comparator. The NOR circuit determines which pulse width is larger of a phase difference detecting signal from the phase comparator or of the delayed reference clock signal. The loop filter has its gain changed in response to an output of the NOR circuit. Thus, it is possible to shorten a synchronization pull-in time and accurately detect a deviation in synchronization. In addition, if a gain control signal is reset on the basis of logic states of a reference clock signal and an internal clock signal in accordance with rising edges and falling edges of the clock signals, it is possible to generate successive gain control signals.