Patents by Inventor Atsuki Inoue

Atsuki Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power supply voltage adjusting device
    Patent number: 8008967
    Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 30, 2011
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Okano, Atsuki Inoue
  • POWER SUPPLY VOLTAGE ADJUSTING DEVICE
    Publication number: 20080191681
    Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.
    Type: Application
    Filed: March 19, 2008
    Publication date: August 14, 2008
    Applicant: Fujitsu Limited
    Inventors: Hiroshi OKANO, Atsuki Inoue
  • Reduced swing charge recycling circuit arrangement and adder including the same
    Patent number: 6803793
    Abstract: A circuit arrangement uses differential pass transistor logic, a low voltage swing and charge recycling to save power, in which the swing voltage is reduced, but the supply voltage is not reduced, thereby maintaining the transistor device current and avoiding speed degradation. SOI devices including an adder, which uses this circuit arrangement, can avoid the body effect to long pass transistor network and improve the speed at lower supply voltage.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: October 12, 2004
    Assignee: Fujitsu Limited
    Inventor: Atsuki Inoue
  • Reduced swing charge recycling circuit arrangement and adder including the same
    Publication number: 20020109530
    Abstract: A circuit arrangement uses differential pass transistor logic, a low voltage swing and charge recycling to save power, in which the swing voltage is reduced, but the supply voltage is not reduced, thereby maintaining the transistor device current and avoiding speed degradation. SOI devices including an adder, which uses this circuit arrangement, can avoid the body effect to long pass transistor network and improve the speed at lower supply voltage.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 15, 2002
    Inventor: Atsuki Inoue
  • Tunneling Josephson element with a blocking layer inert to oxygen
    Patent number: 5155094
    Abstract: A superconductive device and method for the manufacture thereof is disclosed, having a tunneling Josephson element comprising a first oxide superconductor electrode, a blocking layer consisting of a metal substantially inert to oxygen formed on the surface of the oxide superconductor, an insulating thin film layer formed on the blocking layer, and a second superconductor electrode opposing said first electrode formed on the insulating thin film.
    Type: Grant
    Filed: March 29, 1988
    Date of Patent: October 13, 1992
    Assignee: The University of Tokyo
    Inventors: Yoichi Okabe, Atsuki Inoue, Hideomi Koinuma
  • Method for manufacturing a tunneling Josephson element
    Patent number: 5102862
    Abstract: A superconductive device and method for the manufacture thereof is disclosed, having a tunneling Josephson element comprising a first oxide superconductor electrode, a blocking layer consisting of a metal substantially inert to oxygen formed on the surface of the oxide superconductor, an insulating thin film layer formed on the blocking layer, and a second superconductor electrode opposing said first electrode formed on the insulating thin film.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: April 7, 1992
    Assignee: The University of Tokyo
    Inventors: Yoichi Okabe, Atsuki Inoue, Hideomi Koinuma