Patents by Inventor Atsuko Momma
Atsuko Momma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240062803Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.Type: ApplicationFiled: August 18, 2022Publication date: February 22, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: William C. Waldrop, Liang Chen, Shingo Mitsubori, Ryo Fujimaki, Atsuko Momma
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Patent number: 11087806Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: GrantFiled: June 5, 2018Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Patent number: 11062747Abstract: An example apparatus includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.Type: GrantFiled: September 26, 2018Date of Patent: July 13, 2021Assignee: Micron Technology, Inc.Inventor: Atsuko Momma
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Patent number: 10636463Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: GrantFiled: May 22, 2019Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Publication number: 20200098405Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Applicant: Micron Technology, Inc.Inventor: Atsuko Momma
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Publication number: 20190272862Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: ApplicationFiled: May 22, 2019Publication date: September 5, 2019Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Patent number: 10403340Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: GrantFiled: February 7, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Publication number: 20190244644Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Publication number: 20180286470Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: ApplicationFiled: June 5, 2018Publication date: October 4, 2018Applicant: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Patent number: 9997220Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: GrantFiled: August 22, 2016Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Publication number: 20180053538Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: ApplicationFiled: August 22, 2016Publication date: February 22, 2018Applicant: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Patent number: 8213246Abstract: A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a second set of address signals in response to a second type transition of the timing signal. The second set of address signals is different from the first set of address signals.Type: GrantFiled: October 28, 2009Date of Patent: July 3, 2012Assignee: Elpida Memory, Inc.Inventors: Jun Suzuki, Yasuhiro Matsumoto, Atsuko Momma
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Patent number: 8040740Abstract: A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.Type: GrantFiled: October 27, 2009Date of Patent: October 18, 2011Assignee: Elpida Memory, Inc.Inventor: Atsuko Momma
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Publication number: 20100110802Abstract: A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.Type: ApplicationFiled: October 27, 2009Publication date: May 6, 2010Applicant: Elpida Memory, Inc.Inventor: Atsuko Momma
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Publication number: 20100110812Abstract: A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a second set of address signals in response to a second type transition of the timing signal. The second set of address signals is different from the first set of address signals.Type: ApplicationFiled: October 28, 2009Publication date: May 6, 2010Applicant: Elpida Memory, Inc.Inventors: Jun Suzuki, Yasuhiro Matsumoto, Atsuko Momma
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Patent number: 5801554Abstract: A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.Type: GrantFiled: July 3, 1996Date of Patent: September 1, 1998Assignee: Hitachi, Ltd.Inventors: Atsuko Momma, Miki Matsumoto, Kanji Oishi