Patents by Inventor Atsumasa Sawada
Atsumasa Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10404189Abstract: A switching output circuit is provided that enables an accurate control of output power. To achieve the objective, a switching output circuit according to an exemplary aspect of the present invention includes eight switching means, two electric storage means, and a control means, wherein the control means controls the switching means and switches a conduction state and a non-conduction state, by which the power supplied from a direct-current power supply is switched and supplied to an inductive load.Type: GrantFiled: June 15, 2015Date of Patent: September 3, 2019Assignee: NEC CorporationInventors: Osamu Ishibashi, Kazuhisa Sunaga, Atsumasa Sawada, Hideyuki Sugita, Ayami Tanabe
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Patent number: 10135099Abstract: A pulsed discharge device according to an exemplary aspect of the present invention includes a controller configured to determine an interruption time to a discharge time based on a predetermined time ratio between the discharge time and the interruption time when performing a pulsed discharge to repeat alternately a discharge and a pause in discharging of a chemical battery.Type: GrantFiled: April 22, 2015Date of Patent: November 20, 2018Assignee: NEC CorporationInventors: Hiroaki Fukunishi, Kenji Kobayashi, Suguru Watanabe, Osamu Ishibashi, Hiroshi Kajitani, Kazuhisa Sunaga, Hideyuki Sugita, Atsumasa Sawada, Ayami Tanabe
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Publication number: 20170200985Abstract: A pulsed discharge device according to an exemplary aspect of the present invention includes a controller configured to determine an interruption time to a discharge time based on a predetermined time ratio between the discharge time and the interruption time when performing a pulsed discharge to repeat alternately a discharge and a pause in discharging of a chemical battery.Type: ApplicationFiled: April 22, 2015Publication date: July 13, 2017Applicant: NEC CorporationInventors: Hiroaki FUKUNISHI, Kenji KOBAYASHI, Suguru WATANABE, Osamu ISHIBASHI, Hiroshi KAJITANI, Kazuhisa SUNAGA, Hideyuki SUGITA, Atsumasa SAWADA, Ayami TANABE
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Publication number: 20170141700Abstract: A switching output circuit is provided that enables an accurate control of output power. To achieve the objective, a switching output circuit according to an exemplary aspect of the present invention includes eight switching means, two electric storage means, and a control means, wherein the control means controls the switching means and switches a conduction state and a non-conduction state, by which the power supplied from a direct-current power supply is switched and supplied to an inductive load.Type: ApplicationFiled: June 15, 2015Publication date: May 18, 2017Applicant: NEC CorporationInventors: Osamu ISHIBASHI, Kazuhisa SUNAGA, Atsumasa SAWADA, Hideyuki SUGITA, Ayami TANABE
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Patent number: 8913398Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.Type: GrantFiled: September 3, 2013Date of Patent: December 16, 2014Assignee: NEC CorporationInventors: Shinji Watanabe, Nobuhiro Mikami, Junya Sato, Kenichiro Fujii, Katsumi Abe, Atsumasa Sawada
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Patent number: 8625296Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.Type: GrantFiled: June 10, 2011Date of Patent: January 7, 2014Assignee: NEC CorporationInventors: Shinji Watanabe, Nobuhiro Mikami, Junya Sato, Kenichiro Fujii, Katsumi Abe, Atsumasa Sawada
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Publication number: 20140003015Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.Type: ApplicationFiled: September 3, 2013Publication date: January 2, 2014Applicant: NEC CORPORATIONInventors: Shinji WATANABE, Nobuhiro MIKAMI, Junya SATO, Kenichiro FUJII, Katsumi ABE, Atsumasa SAWADA
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Patent number: 8598340Abstract: The present invention can provide new spirooxazine radical derivatives of the following general formula (1) which have chromic property enabling the distinction between the radical species and the cation species on the basis of absorption wavelength:Type: GrantFiled: November 2, 2012Date of Patent: December 3, 2013Assignee: NEC CorporationInventor: Atsumasa Sawada
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Patent number: 8329896Abstract: The present invention can provide new spirooxazine radical derivatives of the following general formula (1) which have chromic property enabling the distinction between the radical species and the cation species on the basis of absorption wavelength:Type: GrantFiled: December 20, 2007Date of Patent: December 11, 2012Assignee: NEC CorporationInventor: Atsumasa Sawada
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Patent number: 8144482Abstract: A circuit board device includes: plurality of wiring boards (101 and 102) in which terminals are provided on the front and back surfaces and vias are provided for connecting the terminals together, an anisotropic conductive member (103) arranged between wiring boards (101 and 102) for connecting the electrodes of one wiring board to the electrodes of another wiring board, a functional block (104) composed of a metal material and arranged between the wiring boards (101 and 102) to enclose anisotropic conductive member (103), and a pair of holding blocks (105 and 106) composed of a metal material arranged to clamp the plurality of wiring boards (101 and 102), wherein the plurality of wiring boards (101 and 102), while in a state of being clamped between the pair of holding blocks (105 and 106), is connected together by the anisotropic conductive member (103) and the terminals provided on each of the wiring boards (101 and 102), the functional block (104), and the holding blocks (105 and 106) are electrically coType: GrantFiled: May 14, 2007Date of Patent: March 27, 2012Assignee: NEC CorporationInventors: Junya Sato, Toru Taura, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Patent number: 8130511Abstract: A circuit board device, a wiring board connecting method, and a circuit board module device are provided for controlling a compression ratio of anisotropically conductive members within an optimal range, for restraining variations in the impact resilient force of the anisotropically conductive members even if an increased number of wiring boards are laminated, for restraining deformations of the wiring board and fluctuations in the impact resilient force of the anisotropically conductive members even if a static external force or the like is applied, for suppressing a linear expansion of the anisotropically conductive members, even if the ambient temperature changes, to increase the stability of electric connections, and for reducing the impact resilient force of the anisotropically conductive members to allow for a reduction in thickness.Type: GrantFiled: May 14, 2007Date of Patent: March 6, 2012Assignee: NEC CorporationInventors: Junya Sato, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Patent number: 8119924Abstract: Stress concentration at the connecting portion of the electronic component and the curved board and the area around the connecting portion is suppressed. In a flexible wiring board, insulation layers (11, 13) and wiring layers (12, 15) are piled up alternately and wiring layers (12, 15) are via-connected each other. The board comprises reinforced area (10a) reinforced against external stress, bending area (10c) bending easier than the reinforced area (10a) by external stress, and a stress relaxation area (10b) provided in area between the reinforced area (10a) and the bending area (10c), bending easier than the reinforced area (10a) but not easier than the bending area (10c) by the external stress, and relaxing the stress carried from the bending area (10c) to the reinforced area (10a).Type: GrantFiled: March 30, 2007Date of Patent: February 21, 2012Assignee: NEC CorporationInventors: Katsumi Abe, Kenichiro Fujii, Atsumasa Sawada
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Patent number: 8119918Abstract: An object of the present invention is to prevent occurrence of an electrical fault such as signal disconnection due to exfoliation between a via and a printed circuit board, via crack, or the like, caused by various stresses that may arise when the printed circuit board is curved. The printed circuit board includes a first wiring layer 11, an electrical insulating base material 12 formed on the first wiring layer 11 and including a via base hole 12a that leads to the first wiring layer 11, and a second wiring layer 16 that is formed on the electrical insulating base material 12 and is electrically connected to the first wiring layer 11 through the via base hole 12a. In a region of the second wiring layer 16 disposed at least in the vicinity of the via base hole 12a, a stress relieving portion 17 is formed which relieves bending stress, tensile stress, compressive stress, and shear stress that may arise when the electrical insulating base material 12 is curved.Type: GrantFiled: September 1, 2006Date of Patent: February 21, 2012Assignee: NEC CorporationInventors: Junya Sato, Shinji Watanabe, Nobuhiro Mikami, Atsumasa Sawada
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Publication number: 20110242780Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.Type: ApplicationFiled: June 10, 2011Publication date: October 6, 2011Applicant: NEC CORPORATIONInventors: Shinji WATANABE, Nobuhiro MIKAMI, Junya SATO, Kenichiro FUJII, Katsumi ABE, Atsumasa SAWADA
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Patent number: 7847389Abstract: Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip has electrodes on a second face thereof. Support blocks, capable of bending and flexing, are placed at two locations on a peripheral edge of a first face of the semiconductor chip. An interposer is placed so as to span the support blocks with the support blocks interposed between itself and the semiconductor chip, and has a wiring pattern in a flexible resin film. Two end portions of the interposer are folded back onto the side of the second face of the semiconductor chip, and the wiring pattern thereof is electrically connected to the electrodes of the semiconductor chip.Type: GrantFiled: November 13, 2006Date of Patent: December 7, 2010Assignee: NEC CorporationInventors: Nobuhiro Mikami, Shinji Watanabe, Junya Sato, Atsumasa Sawada
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Publication number: 20100280241Abstract: The present invention can provide new spirooxazine radical derivatives of the following general formula (1) which have chromic property enabling the distinction between the radical species and the cation species on the basis of absorption wavelength:Type: ApplicationFiled: December 20, 2007Publication date: November 4, 2010Inventor: Atsumasa Sawada
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Publication number: 20100148335Abstract: A highly reliable semiconductor package in which faulty connections do not occur even when an external substrate is curved. The semiconductor package includes a semiconductor chip 1; an interposer substrate 10 arranged so as to enclose the semiconductor chip and having a first electrode pad 14, which is for connecting to an electrode of the semiconductor chip, provided on a wiring layer 12 disposed between insulating layers 11, 13; and a first conductor 2 for connecting the electrode of the semiconductor chip and the electrode pad. A portion of the underside of the interposer substrate 10 is adhered to the interposer substrate 10. A gap 4 is provided between the semiconductor chip 1 and the interposer substrate 10 on the side surface of the semiconductor chip 1.Type: ApplicationFiled: May 28, 2007Publication date: June 17, 2010Applicant: NEC CorporationInventors: Nobuhiro Mikami, Shinji Watanabe, Junya Sato, Atsumasa Sawada
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Publication number: 20090266586Abstract: An object of the present invention is to prevent occurrence of an electrical fault such as signal disconnection due to exfoliation between a via and a printed circuit board, via crack, or the like, caused by various stresses that may arise when the printed circuit board is curved. The printed circuit board includes a first wiring layer 11, an electrical insulating base material 12 formed on the first wiring layer 11 and including a via base hole 12a that leads to the first wiring layer 11, and a second wiring layer 16 that is formed on the electrical insulating base material 12 and is electrically connected to the first wiring layer 11 through the via base hole 12a. In a region of the second wiring layer 16 disposed at least in the vicinity of the via base hole 12a, a stress relieving portion 17 is formed which relieves bending stress, tensile stress, compressive stress, and shear stress that may arise when the electrical insulating base material 12 is curved.Type: ApplicationFiled: September 1, 2006Publication date: October 29, 2009Applicant: NEC CORPORATIONInventors: Junya Sato, Shinji Watanabe, Nobuhiro Mikami, Atsumasa Sawada
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Publication number: 20090161331Abstract: A circuit board device, a wiring board connecting method, and a circuit board module device are provided for controlling a compression ratio of anisotropically conductive members within an optimal range, for restraining variations in the impact resilient force of the anisotropically conductive members even if an increased number of wiring boards are laminated, for restraining deformations of the wiring board and fluctuations in the impact resilient force of the anisotropically conductive members even if a static external force or the like is applied, for suppressing a linear expansion of the anisotropically conductive members, even if the ambient temperature changes, to increase the stability of electric connections, and for reducing the impact resilient force of the anisotropically conductive members to allow for a reduction in thickness.Type: ApplicationFiled: May 14, 2007Publication date: June 25, 2009Inventors: Junya Sato, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Publication number: 20090135573Abstract: A circuit board device includes: plurality of wiring boards (101 and 102) in which terminals are provided on the front and back surfaces and vias are provided for connecting the terminals together, an anisotropic conductive member (103) arranged between wiring boards (101 and 102) for connecting the electrodes of one wiring board to the electrodes of another wiring board, a functional block (104) composed of a metal material and arranged between the wiring boards (101 and 102) to enclose anisotropic conductive member (103), and a pair of holding blocks (105 and 106) composed of a metal material arranged to clamp the plurality of wiring boards (101 and 102), wherein the plurality of wiring boards (101 and 102), while in a state of being clamped between the pair of holding blocks (105 and 106), is connected together by the anisotropic conductive member (103) and the terminals provided on each of the wiring boards (101 and 102), the functional block (104), and the holding blocks (105 and 106) are electrically coType: ApplicationFiled: May 14, 2007Publication date: May 28, 2009Inventors: Junya Sato, Toru Taura, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura