Patents by Inventor Atsuo Uchiyama
Atsuo Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10350788Abstract: Method for slicing a workpiece, including measuring a crystal axis orientation while holding a workpiece with a workpiece holder, setting the workpiece holder to a wire saw in such a manner that the measured crystal axis orientation is maintained, then adjusting a sliced plane orientation, pressing the workpiece against a wire row to slice the workpiece; the workpiece holder includes a portion slidable while holding the workpiece and a portion for fixing the slide portion, after measuring the crystal axis orientation, sliding the slide portion to move to the workpiece holder center in a manner that the measured crystal axis orientation is maintained, fixing the slide portion, setting the workpiece holder to the wire saw, then adjusting the sliced plane orientation, and slicing the workpiece. This enables an orientation measurement without limitation of distance between an orientation measuring instrument and plane to be measured can inhibit warpage deterioration and workpiece breakage.Type: GrantFiled: November 27, 2014Date of Patent: July 16, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Atsuo Uchiyama, Hisakazu Takano, Masahito Saitoh, Hirotoshi Kouzu
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Patent number: 9662805Abstract: A method of resuming operation of a wire saw in which slicing of a workpiece is suspended due to a wire break, including processes of: imparting axial reciprocating motion to a wire while supplying a new line of the wire; and slicing the workpiece into wafers by moving the workpiece downwardly to press the workpiece against the reciprocating wire while supplying a slicing slurry to the wire, the method includes: repairing the broken wire after suspending the slicing of the workpiece before resuming the slicing of the workpiece; and preparing for the slicing in that a diameter of the repaired wire at a position at which the workpiece is to be sliced is matched to the diameter of the wire just before occurrence of the wire break. The method can inhibit the formation of grooves in wafers sliced after the resumption and reduce low-quality production wafers.Type: GrantFiled: December 6, 2013Date of Patent: May 30, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Atsuo Uchiyama, Hisakazu Takano, Hitoshi Sejimo, Yukio Hijirisawa, Daisuke Nakamata
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Publication number: 20160303765Abstract: Method for slicing a workpiece, including measuring a crystal axis orientation while holding a workpiece with a workpiece holder, setting the workpiece holder to a wire saw in such a manner that the measured crystal axis orientation is maintained, then adjusting a sliced plane orientation, pressing the workpiece against a wire row to slice the workpiece; the workpiece holder includes a portion slidable while holding the workpiece and a portion for fixing the slide portion, after measuring the crystal axis orientation, sliding the slide portion to move to the workpiece holder center in a manner that the measured crystal axis orientation is maintained, fixing the slide portion, setting the workpiece holder to the wire saw, then adjusting the sliced plane orientation, and slicing the workpiece. This enables an orientation measurement without limitation of distance between an orientation measuring instrument and plane to be measured can inhibit warpage deterioration and workpiece breakage.Type: ApplicationFiled: November 27, 2014Publication date: October 20, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Atsuo UCHIYAMA, Hisakazu TAKANO, Masahito SAITOH, Hirotoshi KOUZU
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Publication number: 20150328800Abstract: A method of resuming operation of a wire saw in which slicing of a workpiece is suspended due to a wire break, including processes of: imparting axial reciprocating motion to a wire while supplying a new line of the wire; and slicing the workpiece into wafers by moving the workpiece downwardly to press the workpiece against the reciprocating wire while supplying a slicing slurry to the wire, the method includes: repairing the broken wire after suspending the slicing of the workpiece before resuming the slicing of the workpiece; and preparing for the slicing in that a diameter of the repaired wire at a position at which the workpiece is to be sliced is matched to the diameter of the wire just before occurrence of the wire break. The method can inhibit the formation of grooves in wafers sliced after the resumption and reduce low-quality production wafers.Type: ApplicationFiled: December 6, 2013Publication date: November 19, 2015Inventors: Atsuo UCHIYAMA, Hisakazu TAKANO, Hitoshi SEJIMO, Yukio HIJIRISAWA, Daisuke NAKAMATA
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Patent number: 9163327Abstract: Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×1010 atoms/cm2 or less. In order to manufacture such a wafer as contains a small amount of boron attached on the wafer surface, the wafer is treated in an atmosphere of boron concentration of 15 ng/m3 or less. Boron-less filters and boron adsorbing filters are used as filters in a clean room and the like so as to lower the boron concentration in the atmosphere.Type: GrantFiled: August 2, 2012Date of Patent: October 20, 2015Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumiaki Maruyama, Naoki Naito, Atsuo Uchiyama
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Publication number: 20120298995Abstract: Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×1010 atoms/cm2 or less. In order to manufacture such a wafer as contains a small amount of boron attached on the wafer surface, the wafer is treated in an atmosphere of boron concentration of 15 ng/m3 or less. Boron-less filters and boron adsorbing filters are used as filters in a clean room and the like so as to lower the boron concentration in the atmosphere.Type: ApplicationFiled: August 2, 2012Publication date: November 29, 2012Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Fumiaki Maruyama, Naoki Naito, Atsuo Uchiyama
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Patent number: 8273146Abstract: Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×1010 atoms/cm2 or less. In order to manufacture such a wafer as contains a small amount of boron attached on the wafer surface, the wafer is treated in an atmosphere of boron concentration of 15 ng/m3 or less. Boron-less filters and boron adsorbing filters are used as filters in a clean room and the like so as to lower the boron concentration in the atmosphere.Type: GrantFiled: September 20, 2000Date of Patent: September 25, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumiaki Maruyama, Naoki Naito, Atsuo Uchiyama
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Patent number: 5395788Abstract: The present invention provides a method of making a semiconductor substrate having an SOI structure by temporarily bonding together two wafers having different thermal expansion coefficients to allow thinning of at least one of the wafers by chemical and/or mechanical treatment(s) to reduce the risk of strain, separation, cracks to the wafers followed by one or more heat treating steps to fully bond the wafers together. The method can produce semiconductor substrate having an SOI structure which can provide a silicon layer thin enough to allow various integrated circuits, or TFL-LCD or the like to be formed.Type: GrantFiled: September 3, 1993Date of Patent: March 7, 1995Assignee: Shin Etsu Handotai Co., Ltd.Inventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
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Patent number: 5266824Abstract: The present invention provides a semiconductor substrate which is formed by bonding wafers together by heat treatment without causing the substrate to be thermally damaged to have thermal strain, separation, cracks, etc. due to the difference in the thermal expansion coefficient of the wafers, and particularly a semiconductor substrate having an SOI structure which can provide a silicon film thin enough to allow various integrated circuits or TFT-LCD to be formed In the present invention, after wafers are bonded temporarily in a low temperature range, one of the wafers is made thin by chemical treatment, then the wafers were bonded fully by heat treatment in a temperature range (where the thermal expansion coefficient of the wafer are not affected) higher than the above low temperature range, and then said one wafer can be made thinner by mechanical grinding or polishing mechano-chemically.Type: GrantFiled: March 16, 1992Date of Patent: November 30, 1993Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
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Patent number: 5213657Abstract: A Si single crystal thin film is classified according to the thickness into several areas such that the areas where the thin film is thicker is made oxide layer-free and the areas where the thin film is thinner is covered with oxide layer. Then, oxidation is conducted so that the thicker the thin film the lower the Si interface becomes, utilizing the different growth rates of the oxide layer in these areas. The thin film surface with a resulting staircase configuration is then leveled by the subsequent polishing treatment. In other method, oxide layer is formed in such way that the areas with a thicker thin film thickness will have a thinner oxide layer and the areas with a thinner thin film thickness will have a thicker oxide layer, and oxidation is conducted such that the thicker the thin film the lower the Si interface becomes.Type: GrantFiled: July 29, 1992Date of Patent: May 25, 1993Assignee: Shin-Etsu Handotai Kabushiki KaishaInventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
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Patent number: 5152857Abstract: In a method for preparing a substrate for semiconductor device, the substrate is prepared either by directly bonding a bonding wafer to a base wafer or by bonding the bonding wafer to the base wafer with an oxide film formed on at least the bonding surface of the bonding wafer or the bonding surface of the base wafer to make finished semiconductor devices with an SOI structure. Prior to the bonding operation, the bonding wafer and the base wafer are subjected to the steps of (1) making the diameter of the bonding wafer smaller than the diameter of the base wafer, (2) setting the beveling width of the back side (bonding side) of the bonding wafer at 50 microns or less, and (3) beveling the front side of said base wafer so that the bonding surface of the base wafer is equal in size to the bonding surface of the bonding wafer.Type: GrantFiled: March 21, 1991Date of Patent: October 6, 1992Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tatsuo Ito, Atsuo Uchiyama, Masao Fukami