Abstract: A novel plastic molded chip carrier package for an integrated circuit chip has a carrier member molded of a plastic material to which are integrally embedded a plurality of I/O pins and a conductor member for interconnection between the terminals of the chip and the corresponding I/O pins to provide a unitary construction obtained at a single molding process. This plastic molded chip carrier package is preferred to have integral positioning studs which project in the same direction of the I/O pins for abutment against a printed circuit board for mounting the package in a spaced relation thereto with the I/O pins plugged into metallized through holes provided in the board.

Abstract: An improved plastic molded chip carrier package for a semiconductor chip has a plurality of I/O pins arranged on a pin grid array. The pin grid array comprises at least two rows of the I/O pins disposed along the sides of the chip in such a manner that the I/O pins are staggered with respect to those in the other row. The staggered arrangement of the I/O pins makes it easy to provide electrical interconnection between the I/O ports on the chip and the corresponding I/O pins without requiring an elaborate or crowded wiring or connection lines. This is particularly effective when an increased number of the I/O pins are required to be included in the limited area of the chip carrier.