Patents by Inventor Atsushi Kagisawa

Atsushi Kagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8004040
    Abstract: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: August 23, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisao Ichijo, Alberto Adan, Kazushi Naruse, Atsushi Kagisawa
  • Publication number: 20090159970
    Abstract: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 25, 2009
    Inventors: Hisao Ichijo, Alberto Adan, Kazushi Naruse, Atsushi Kagisawa