Patents by Inventor Atsushi Kitagawa
Atsushi Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220041656Abstract: Disclosed are a novel compound having a higher angiogenic effect than that of a known peptide-based angiogenic agent, and an angiogenic agent including the novel compound. The compound is represented by the following formula [1]: Cyclic(Cys-O2Oc-SVV(F/Y)GLRG-Cys)-NH2 (wherein the number of oxyethylene units, represented by O2Oc, is within the range of 2 to 6), the following formula [II]: Cyclic(O2Oc-SVV(F/Y)GLRQ)-NH2 [II] (wherein the number of oxyethylene units, represented by O2Oc, is within the range of 2 to 6), or the following formula [III]: O2Oc-SVV(F/Y)GLR-NH2 [III] (wherein the number of oxyethylene units, represented by O2Oc, is within the range of 2 to 6).Type: ApplicationFiled: October 31, 2019Publication date: February 10, 2022Applicant: HiPep LaboratoriesInventors: Kiyoshi NOKIHARA, Yuki TOMINAGA, Atsushi KITAGAWA, Shun NOKIHARA
-
Patent number: 10483966Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.Type: GrantFiled: December 19, 2018Date of Patent: November 19, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takahiro Uehara, Takuya Ishii, Hiroyuki Handa, Atsushi Kitagawa, Takeshi Tanaka
-
Publication number: 20190149148Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.Type: ApplicationFiled: December 19, 2018Publication date: May 16, 2019Inventors: Takahiro UEHARA, Takuya ISHII, Hiroyuki HANDA, Atsushi KITAGAWA, Takeshi TANAKA
-
Patent number: 10205449Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.Type: GrantFiled: March 19, 2018Date of Patent: February 12, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takahiro Uehara, Takuya Ishii, Hiroyuki Handa, Atsushi Kitagawa, Takeshi Tanaka
-
Publication number: 20180212509Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.Type: ApplicationFiled: March 19, 2018Publication date: July 26, 2018Inventors: Takahiro UEHARA, Takuya ISHII, Hiroyuki HANDA, Atsushi KITAGAWA, Takeshi TANAKA
-
Patent number: 10033275Abstract: A DC-DC converter module includes a module substrate on which switching transistors and a controller IC chip are mounted, stud terminals mounted on a surface of the module substrate, and an inductor attached to the stud terminals such that the inductor faces the module substrate. In a plan view, the switching transistors are arranged within an area where the inductor overlaps the module substrate, whereas at least a portion of the controller IC chip is arranged outside the area.Type: GrantFiled: February 2, 2016Date of Patent: July 24, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Takuya Ishii, Atsushi Kitagawa, Tadata Hatanaka
-
Patent number: 9812964Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: GrantFiled: June 14, 2016Date of Patent: November 7, 2017Assignee: ROHM CO., LTD.Inventor: Atsushi Kitagawa
-
Publication number: 20160294288Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Applicant: ROHM CO., LTD.Inventor: Atsushi KITAGAWA
-
Patent number: 9391038Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: GrantFiled: September 23, 2014Date of Patent: July 12, 2016Assignee: ROHM CO., LTD.Inventor: Atsushi Kitagawa
-
Publication number: 20160164417Abstract: A DC-DC converter module includes a module substrate on which switching transistors and a controller IC chip are mounted, stud terminals mounted on a surface of the module substrate, and an inductor attached to the stud terminals such that the inductor faces the module substrate. In a plan view, the switching transistors are arranged within an area where the inductor overlaps the module substrate, whereas at least a portion of the controller IC chip is arranged outside the area.Type: ApplicationFiled: February 2, 2016Publication date: June 9, 2016Inventors: Takuya ISHII, Atsushi KITAGAWA, Tadata HATANAKA
-
Publication number: 20150021768Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: ApplicationFiled: September 23, 2014Publication date: January 22, 2015Inventor: Atsushi KITAGAWA
-
Patent number: 8872577Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: GrantFiled: February 26, 2014Date of Patent: October 28, 2014Assignee: Rohm Co., Ltd.Inventor: Atsushi Kitagawa
-
Publication number: 20140175648Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact, with the IC socket of the semiconductor device. Each pair of nearest neighbors, of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: ROHM CO., LTD.Inventor: Atsushi KITAGAWA
-
Patent number: 8704357Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: GrantFiled: October 5, 2011Date of Patent: April 22, 2014Assignee: Rohm Co., Ltd.Inventor: Atsushi Kitagawa
-
Patent number: 8659514Abstract: LED drivers specially directed to LED matrix driver's ghost image prevention is disclosed. The LED driver receives an external input and decodes the input to produce a time multiplex timing on turning on an LED array. The LED driver inserts a dead time to the outputs and during this time the ghost image prevention circuit discharges the output stray capacitances to a predetermined level.Type: GrantFiled: January 11, 2011Date of Patent: February 25, 2014Assignees: Panasonic Corporation, Panasonic Semiconductor Asia Pte. Ltd.Inventors: Etsuji Sato, Atsushi Kitagawa, Yoshihito Kawakami, Chun Kiong Leslie Khoo, Ulysses Ramos Lopez, Narciso Repollo Semira, Jiong Fu
-
Patent number: 8305011Abstract: Multiple LED terminals are provided to multiple LEDs, respectively. Each of these LED terminals is connected to the anode of the corresponding LED. A booster circuit boosts an input voltage. Multiple constant current sources are provided to the multiple LEDs, respectively. One terminal of each of the constant current sources is connected to the corresponding one of the LEDs via the corresponding one of the LED terminals. Multiple switches are provided to the multiple constant current sources, respectively, each of which selectively outputs a voltage selected from the input voltage and the output voltage of the booster circuit to the corresponding constant current source. A control circuit monitors each of the voltages at the multiple LED terminals, and controls the connection state of each of the switches based upon the corresponding voltage.Type: GrantFiled: July 3, 2008Date of Patent: November 6, 2012Assignee: Rohm Co., Ltd.Inventors: Atsushi Kitagawa, Kunihiro Komiya
-
Publication number: 20120176062Abstract: LED drivers specially directed to LED matrix driver's ghost image prevention is disclosed. The LED driver receives an external input and decodes the input to produce a time multiplex timing on turning on an LED array. The LED driver inserts a dead time to the outputs and during this time the ghost image prevention circuit discharges the output stray capacitances to a predetermined level.Type: ApplicationFiled: January 11, 2011Publication date: July 12, 2012Applicants: PANASONIC SEMICONDUCTOR ASIA PTE., LTD., PANASONIC CORPORATIONInventors: Etsuji SATO, Atsushi KITAGAWA, Yoshihito KAWAKAMI, Chun Kiong Leslie KHOO, Ulysses Ramos LOPEZ, Narciso Repollo SEMIRA, Jiong FU
-
Publication number: 20120032713Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: ApplicationFiled: October 5, 2011Publication date: February 9, 2012Applicant: ROHM CO., LTD.Inventor: Atsushi KITAGAWA
-
Patent number: 8063494Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: GrantFiled: June 30, 2005Date of Patent: November 22, 2011Assignee: Rohm Co., Ltd.Inventor: Atsushi Kitagawa
-
PWM power supply apparatus having a controlled duty ratio without causing overall system oscillation
Patent number: 7893667Abstract: A direct-current stabilized power supply apparatus according to the present invention includes offsetting means that keeps a slope voltage (Vslp) shifted from the ground potential to a higher potential by a predetermined offset voltage ?V so that the lower limit level of the slope voltage (Vslp) is higher than that of an error voltage (Verr). With this configuration, it is possible to provide a direct-current stabilized power supply apparatus that can appropriately control a duty ratio without causing oscillation or the like in the overall system, and also to provide an electrical device incorporating such a power supply apparatus.Type: GrantFiled: August 2, 2006Date of Patent: February 22, 2011Assignee: Rohm Co., Ltd.Inventors: Atsushi Kitagawa, Hiroaki Asazu