Patents by Inventor Atsushi Matsuda
Atsushi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180046287Abstract: An input device that enables wires to be bent together with a base material without deteriorating translucency and conductivity of the wires has: a base material having translucency and flexibility; first electrode parts and second electrode parts, both having translucency, that are provided in a sensing region on the base material; and lead wires that are electrically continuous to the first electrode parts and second electrode parts, the lead wires extending, on the base material, from the sensing region to a peripheral region. A bent portion is provided in the peripheral region on the base material. Each lead wire has a flexible laminated body provided on the bent portion. The flexible laminated body has a first amorphous ITO layer provided on the base material, a conductive layer provided on the first amorphous ITO layer, and a second amorphous ITO layer provided on the conductive layer.Type: ApplicationFiled: October 12, 2017Publication date: February 15, 2018Inventors: Suguru WADA, Junji HASHIDA, Toru SAWADA, Atsushi MATSUDA, Toru TAKAHASHI, Minoru SATO
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Publication number: 20180034469Abstract: A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.Type: ApplicationFiled: July 21, 2017Publication date: February 1, 2018Inventor: Atsushi MATSUDA
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Publication number: 20170336413Abstract: A method of evaluating disease activity of rheumatoid arthritis with good sensitivity by a simple method, and a kit for use in the method. It provides a Jacalin-binding O-linked oligosaccharide epitope as a negative marker for diagnosing rheumatoid arthritis, and enables more accurate assessment of disease condition by more objectively determining disease activity of rheumatoid arthritis using the amount of variation of a value obtained by multiplying the amount of MMP-3 in the blood or the amount of bound MMP-3 and ABA, ACA, or ACG in the blood by the reciprocal of the amount of bound MMP-3 and Jacalin in the blood. Through the discovery that an LEL or STL-reactive sugar chain on MMP-3 in the blood is a sugar chain marker for diagnosing polymyalgia rheumatica and relapsing polychondritis, the present invention also provides a method for accurate diagnosis of polymyalgia rheumatica and relapsing polychondritis.Type: ApplicationFiled: October 29, 2015Publication date: November 23, 2017Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, KEIO UNIVERSITY, GLYCOBIOMARKER LEADING INNOVATION CO. LTD.Inventors: Atsushi Kuno, Atsushi Matsuda, Hisashi Narimatsu, Tsutomu Takeuchi, Katsuya Suzuki, Masaru Taskeshita
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Publication number: 20170219590Abstract: The problem addressed by the present invention is to provide a marker for detecting hepatocellular carcinoma, wherein the hepatocellular carcinoma marker comprises a glycoprotein that first becomes present in the liver with the occurrence of cancer, without depending on changes in the state of the liver.Type: ApplicationFiled: July 22, 2015Publication date: August 3, 2017Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Atsushi KUNO, Takashi SATO, Atsushi MATSUDA, Hisashi NARIMATSU, Hiroyuki KAJI, Akira TOGAYACHI, Ken SHIRABE, Yoshihiko MAEHARA
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Patent number: 9172385Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.Type: GrantFiled: October 7, 2014Date of Patent: October 27, 2015Assignee: SOCIONEXT INC.Inventor: Atsushi Matsuda
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Patent number: 9083361Abstract: An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.Type: GrantFiled: April 28, 2014Date of Patent: July 14, 2015Assignee: FUJITSU LIMITEDInventor: Atsushi Matsuda
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Publication number: 20150130520Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.Type: ApplicationFiled: October 7, 2014Publication date: May 14, 2015Inventor: Atsushi MATSUDA
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Patent number: 8981974Abstract: A first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element, to a first delay element. A second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element, to a second delay element. After the two clock signals are respectively taken in the first delay elements and the second delay elements by putting the first and second switching units into the first state, the control unit puts the first and second switching units into the second state. An output unit outputs a phase difference obtained by decoding values stored in FFs in the second state.Type: GrantFiled: September 8, 2014Date of Patent: March 17, 2015Assignee: Fujitsu LimitedInventors: Win Chaivipas, Atsushi Matsuda
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Publication number: 20140375486Abstract: A first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element, to a first delay element. A second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element, to a second delay element. After the two clock signals are respectively taken in the first delay elements and the second delay elements by putting the first and second switching units into the first state, the control unit puts the first and second switching units into the second state. An output unit outputs a phase difference obtained by decoding values stored in FFs in the second state.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Win CHAIVIPAS, Atsushi MATSUDA
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Patent number: 8854102Abstract: A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.Type: GrantFiled: November 1, 2013Date of Patent: October 7, 2014Assignee: Fujitsu LimitedInventors: Win Chaivipas, Atsushi Matsuda
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Publication number: 20140232473Abstract: An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: FUJITSU LIMITEDInventor: Atsushi Matsuda
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Patent number: 8736327Abstract: A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.Type: GrantFiled: June 24, 2009Date of Patent: May 27, 2014Assignee: Fujitsu LimitedInventor: Atsushi Matsuda
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Patent number: 8709328Abstract: This method for forming ventilation holes in an electrode plate includes: a roughening step of roughening a surface of an electrode plate for a plasma processing apparatus such that a center line average roughness Ra becomes in a range of 0.2 ?m to 30 ?m; and a ventilation hole forming step of irradiating a laser beam having a wavelength within a range of 200 nm to 600 nm on a roughened surface of the electrode plate so as to form ventilation holes in the electrode plate which pass through the electrode plate in a thickness direction, wherein in the ventilation hole forming step, a focus spot of the laser light is swirled along a planar direction of the electrode plate so as to form a circular irradiation area, and while moving the irradiation area along a planar direction of the electrode plate in a circular movement, the focus spot of the laser light is shifted in a thickness direction of the electrode plate.Type: GrantFiled: October 6, 2010Date of Patent: April 29, 2014Assignee: Mitsubishi Materials CorporationInventors: Satoshi Fujita, Atsushi Matsuda
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Publication number: 20140055181Abstract: A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.Type: ApplicationFiled: November 1, 2013Publication date: February 27, 2014Applicant: FUJITSU LIMITEDInventors: Win CHAIVIPAS, Atsushi MATSUDA
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Patent number: 8638147Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock having a frequency depending on an input code; a phase comparison section configured to output a phase difference signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; a low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.Type: GrantFiled: August 12, 2013Date of Patent: January 28, 2014Assignee: Fujitsu LimitedInventor: Atsushi Matsuda
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Publication number: 20130328604Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock haying a frequency depending on an input code; phase comparison section configured to output a phase differences signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: FUJITSU LIMITEDInventor: Atsushi MATSUDA
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Patent number: 8557602Abstract: Disclosed are a method for early, sensitively and reliably detecting and distinguishing intrahepatic cholangiocarcinoma in a malignant tumor occurring primarily in the liver in a simple way, and a kit thereof. In the method, a glycan biomarker consisting of a lectin WFA (Wisteria floribunda Agglutinin)-binding glycoprotein derived from intrahepatic cholangiocarcinoma is used as a cancer marker to detect intrahepatic cholangiocarcinoma by detecting the cancer marker in a test specimen. The method for detecting intrahepatic cholangiocarcinoma can clearly differentiate intrahepatic cholangiocarcinoma from hepatocellular carcinoma and enables early detection and determination with a performance clinically acceptable in terms of applicability, sensitivity and precision.Type: GrantFiled: February 23, 2010Date of Patent: October 15, 2013Assignees: National Institute of Advanced Industrial Science and Technology, University of TsukubaInventors: Atsushi Kuno, Jun Hirabayashi, Atsushi Matsuda, Hisashi Narimatsu, Yuzuru Ikehara, Junichi Shoda, Toru Kawamoto
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Patent number: 8384451Abstract: A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.Type: GrantFiled: July 26, 2011Date of Patent: February 26, 2013Assignee: Fujitsu LimitedInventor: Atsushi Matsuda
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Publication number: 20120187605Abstract: This method for forming ventilation holes in an electrode plate includes: a roughening step of roughening a surface of an electrode plate for a plasma processing apparatus such that a center line average roughness Ra becomes in a range of 0.2 ?m to 30 ?m; and a ventilation hole forming step of irradiating a laser beam having a wavelength within a range of 200 nm to 600 nm on a roughened surface of the electrode plate so as to form ventilation holes in the electrode plate which pass through the electrode plate in a thickness direction, wherein in the ventilation hole forming step, a focus spot of the laser light is swirled along a planar direction of the electrode plate so as to form a circular irradiation area, and while moving the irradiation area along a planar direction of the electrode plate in a circular movement, the focus spot of the laser light is shifted in a thickness direction of the electrode plate.Type: ApplicationFiled: October 6, 2010Publication date: July 26, 2012Applicant: Mitsubishi Materials CorporationInventors: Satoshi Fujita, Atsushi Matsuda
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Publication number: 20120092052Abstract: A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.Type: ApplicationFiled: June 24, 2009Publication date: April 19, 2012Applicant: FUJITSU LIMITEDInventor: Atsushi Matsuda