Abstract: A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.

Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.

Abstract: A PLL circuit includes a phase comparator, an integrator path, a proportional path, a current controlled oscillator, a divider, and a double integrator path. The double integrator path includes an intermittent operation gm amplifier, a filter circuit, and a voltage-current conversion circuit. The intermittent operation gm amplifier receives an output voltage of a filter circuit. When a pulse CLK for an intermittent operation is ON, the intermittent operation gm amplifier outputs its voltage to the filter circuit. When the pulse CLK for the intermittent operation is OFF, the intermittent operation gm amplifier does not output the output voltage of the filter circuit to the filter circuit. Even when the pulse CLK for the intermittent operation is OFF, an input potential of the voltage-current conversion circuit is held by the filter circuit, and a current to the current controlled oscillator flows. This makes it possible to oscillate at a high frequency without increasing an area of the filter circuit.

Abstract: A PLL circuit includes a phase comparator, an integrator path, a proportional path, a current controlled oscillator, a divider, and a double integrator path. The double integrator path includes an intermittent operation gm amplifier, a filter circuit, and a voltage-current conversion circuit. The intermittent operation gm amplifier receives an output voltage of a filter circuit. When a pulse CLK for an intermittent operation is ON, the intermittent operation gm amplifier outputs its voltage to the filter circuit. When the pulse CLK for the intermittent operation is OFF, the intermittent operation gm amplifier does not output the output voltage of the filter circuit to the filter circuit. Even when the pulse CLK for the intermittent operation is OFF, an input potential of the voltage-current conversion circuit is held by the filter circuit, and a current to the current controlled oscillator flows. This makes it possible to oscillate at a high frequency without increasing an area of the filter circuit.

Abstract: An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

Abstract: An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

Abstract: An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

Abstract: An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

Abstract: A high-precision ?? modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.

Abstract: A high-precision ?? modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.