Abstract: A sheet conveying device for conveying a sheet includes a displacement-amount detector configured to detect an amount of displacement of a conveyed sheet from a conveyance reference in a width direction being substantially perpendicular to a sheet conveying direction and a plurality of sheet conveying roller portions configured to be shiftable in a direction substantially perpendicular to the sheet conveying direction while pinching the sheet having the amount of displacement detected by the displacement-amount detector. Before the sheet reaches the sheet conveying roller portions, the sheet conveying roller portions are shifted based on the amount of displacement detected by the displacement-amount detector from a conveyance-reference position in a direction in which the sheet is displaced. After the sheet reaches the sheet conveying roller portions, the sheet conveying roller portions are shifted while pinching the sheet so as to reduce the amount of displacement.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit.

Abstract: A fixing apparatus includes a fixing rotary body; a rotary body provided with an interval from the fixing rotary body; an endless belt rotating in a condition in which it is wound around the fixing rotary body and the rotary body; a pressure rotary body which makes a pressure contact with the fixing roller across the endless belt; a heater for heating a recording material conveyed by the endless belt; a cooling unit for cooling a recording material conveyed by the endless belt and heated by the heater; and an error detecting member for detecting an error in conveyance of the recording material. When an error is detected in the downstream of the cooling unit by the error detecting member, the recording material is stopped after the recording material on the endless belt is conveyed to a position in which the cooling unit cools the recording material.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of the pairs including a first bit line, a second bit line, a memory cell coupled to the first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.

Abstract: The problems to be solved by the invention are to provide an inorganic composition for obtaining an inorganic product which is excellent in physical property such as installing property, and which is economical price, as well as a process for manufacturing the product. Namely, the present invention provides, as a means to solve the conventional problems, an inorganic composition comprising the following raw materials: a hydraulic inorganic material, a siliceous material and a woody reinforcement, wherein the hydraulic inorganic material is a cementitious material, the siliceous material is a mixture of a rough particle size of siliceous material and a finely particle size of siliceous material, and the woody reinforcement is a wood powder and a pulp. The effects of the present invention, it is possible to obtain an inorganic product which is excellent in physical property such as installing property, and which is economical price.

Abstract: There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF.

Abstract: When a comparative determination portion determines that passage of a sheet through a reference position is lagged based on a detecting signal from a passing timing detection unit, a sheet conveying speed of a skew feeding correction roller on the same side as that of a sensor which detects the lagged sheet in two sensors is increased to correct sheet skew feeding. When the comparative determination portion determines that passage of a sheet through a reference position is leaded, the sheet conveying speed of the skew feeding correction roller on the same side as that of a sensor which detects the leaded sheet in the two sensors is reduced to correct sheet skew feeding.

Abstract: A power tool includes: a stator having a substantially cylindrical yoke and a plurality of permanent magnets that are firmly fixed to an inner surface of the yoke and circumferentially spaced from each other by a first gap; a rotor inserted inside the permanent magnets at a second gap radially; an outer frame portion that accommodates the stator and the rotor; a ventilation hole formed in the outer frame portion to place the first and second gaps in communication with an atmosphere; and a dustproof member comprising a ferromagnetic material, which is mounted in contact with the stator and has a protruding portion located in a passage going from the first and second gaps to the atmosphere via the ventilation hole.

Abstract: A nitride semiconductor device enabiling to supress current collapse and manufacturing method thereof including a III-V group nitride semiconductor layer formed of III group elements includes at least one element from the group consisting of gallium, aluminum, boron and indium, and V group elements including at least nitrogen from the group consisting of nitrogen, phosphorous and arsenic, comprising a first nitride semiconductor layer made of said III-V group nitride semiconductor layer deposited on a substrate, a second nitride semiconductor layer comprising said III-V group nitride semiconductor layer and a control electrode making Schottky contact with the first nitride semiconductor layer being exposed through removing a portion of the second semiconductor layer.

Abstract: A CMOS sensor scans an image that is either on a transfer material carrier or on a transfer material that is placed on the transfer material carrier. A sampling timing controller samples an image signal at a predetermined sampling rate and computes a position of a predetermined pattern contained within the sampled image signal. A speed computation processor computes a moving speed of either the transfer material carrier or the transfer material, based on the position of the predetermined pattern thus sampled at the predetermined sampling rate and computed, as well as the predetermined sampling rate. The image region that the CMOS sensor scans is determined in accordance with the rotational speed of the drive motor and the sampling rate.

Abstract: A battery pack has a housing, a battery cell containing part which is provided in the housing and contains battery cells, a plurality of first terminals which are electrically connected to the battery cell containing part, a plurality of second terminals through which control signals for controlling at least one of charge and discharge of the battery cells contained in the battery cell containing part are transmitted. The first and second terminals can be pressure fitted to corresponding terminals of the body of the apparatus. The first and second terminals are so constructed that when the housing has been attached to the body of the apparatus, fitting pressure exerted on the first terminals is higher than fitting pressure exerted on the second terminals.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: The present invention is to provide a gene having asymmetric hydrolase activity which is useful for synthesis of an optically active carboxylic acid, its antipode ester, and lactone, and a hydroxycarboxylic ester asymmetric hydrolase enzyme (EnHCH) derived from Enterobacter sp. DS-S-75 strain (FERM BP-5494) which is bacteria belonging to the genus Enterobacter, a EnHCH gene shown by base sequence of SEQ. ID. NO: 1, a gene encoding a protein having an amino acid sequence of SEQ. ID. NO: 2, and E. coli DH5? (pKK-EnHCH) deposited to International Patent Organism Depositary, National Institute of Advanced Industrial Science and Technology as a deposition No. FERM BP-08466.

Abstract: A power tool includes a brushless motor, a cooling fan, and a driving unit in a housing. The brushless motor is provided in the housing and having a rotary shaft. The cooling fan is attached to the rotary shaft in the housing, and rotatable together with the rotary shaft. The driving unit is provided in the housing for driving the motor. The driving unit includes an inverter circuit having a circuit board and a plurality of switching elements mounted on the circuit board. The circuit board is positioned on an opposite side to the motor with respect to the cooling fan. The plurality of switching elements is positioned around the cooling fan in a circumferential direction about the rotary shaft.

Abstract: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus and arsenic, including a first nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on a substrate, a second nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on the first nitride semiconductor and not containing aluminum and a control electrode making Schottky contact with the second nitride semiconductor layer wherein the second nitride semiconductor layer includes a film whose film forming temperature is lower than the first nitride semiconductor layer.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus and arsenic, including a first nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on a substrate, a second nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on the first nitride semiconductor and not containing aluminum and a control electrode making Schottky contact with the second nitride semiconductor layer wherein the second nitride semiconductor layer includes a film whose film forming temperature is lower than the first nitride semiconductor layer.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.