Abstract: An operation path generation unit (210) generates an operation quantity time series for an actuator (111) based on a measurement state quantity output from a state sensor (101). A predictive model unit (220) generates a state quantity predictive time series by calculating a predictive model by using as an input the measurement state quantity and the operation quantity time series. A neural network unit (230) corrects the state quantity predictive time series by performing arithmetic operation of a neural network, by using as an input a measurement environment quantity output from an environment sensor (102) and the state quantity predictive time series. A state quantity evaluation unit (240) generates an evaluation result for the state quantity time series after the correction. The operation path generation unit outputs an operation quantity at the head of the operation quantity time series to the actuator when the evaluation result fulfils an appropriate criterion.

Abstract: In a computer apparatus (100), an output management unit (200) determines for each data processing system configured with an OS (160), an application (170), and a management unit (180), depending on the state of the each processing system, whether or not a communication between each data processing system and a device is permitted. Further, the output management unit (200) controls for each data processing system the communication between each data processing system and the device in accordance with a determination result.

Abstract: At start-up of a computer apparatus, a CPU executes a first initialization procedure included in a RAS module to initialize resources to be used by the RAS module. After execution of the first initialization procedure, the CPU executes an initialization procedure included in an OS to initialize resources to be used by the OS. After execution of the initialization procedure, the CPU executes a second initialization procedure included in the RAS module to copy an interrupt determining part included in the OS to the RAS module, and to set the interrupt detection unit such that upon detecting an interrupt the interrupt detection unit calls an interrupt determining part copied to the RAS module, instead of the interrupt determining part in the OS.

Abstract: In a computer apparatus (100), an output management unit (200) determines for each data processing system configured with an OS (160), an application (170), and a management unit (180), depending on the state of the each processing system, whether or not a communication between each data processing system and a device is permitted. Further, the output management unit (200) controls for each data processing system the communication between each data processing system and the device in accordance with a determination result.

Abstract: At start-up of a computer apparatus, a CPU executes a first initialization procedure included in a RAS module to initialize resources to be used by the RAS module. After execution of the first initialization procedure, the CPU executes an initialization procedure included in an OS to initialize resources to be used by the OS. After execution of the initialization procedure, the CPU executes a second initialization procedure included in the RAS module to copy an interrupt determining part included in the OS to the RAS module, and to set the interrupt detection unit such that upon detecting an interrupt the interrupt detection unit calls an interrupt determining part copied to the RAS module, instead of the interrupt determining part in the OS.

Abstract: When an error occurs while a memory dump performing unit of a processor core is storing in an HDD device data of a memory device which is a shared memory, a memory dump error detection unit detects a memory dump error. A core coordination unit notifies the memory dump error to a core coordination unit of a processor core. Upon being notified by the core coordination unit of the memory dump error in the memory dump performing unit, a memory dump performing unit of the processor core stores in the HDD device the data of the memory device in place of the memory dump performing unit.

Abstract: When an error occurs while a memory dump performing unit of a processor core is storing in an HDD device data of a memory device which is a shared memory, a memory dump error detection unit detects a memory dump error. A core coordination unit notifies the memory dump error to a core coordination unit of a processor core. Upon being notified by the core coordination unit of the memory dump error in the memory dump performing unit, a memory dump performing unit of the processor core stores in the HDD device the data of the memory device in place of the memory dump performing unit.

Abstract: A data processing device includes flash memory; nonvolatile memory having an erasure block buffer in which there are stored data recorded in an erasure-unit region of the flash memory; a write control controller for writing into the erasure block buffer write request data, which are to be written into the flash memory; a save unit for saving non-changing data stored in the flash memory to the erasure block buffer; an erasure instruction unit for instructing erasure of the data from the flash memory; and a write unit for writing the data recorded in the erasure block buffer to the flash memory.

Abstract: A data processing device includes flash memory 101; nonvolatile memory 102 having an erasure block buffer 103 in which there are stored data recorded in an erasure-unit region of the flash memory 101; a write controller 111 for writing into the erasure block buffer 103 write request data which are to be written into the flash memory 101; a save unit 112 for saving non-changing data stored in the flash memory 101 to the erasure block buffer 103; an erasure instruction unit 301 for instructing erasure of the data from the erasure-unit region of flash memory 101; and a write unit for writing the data recorded in the erasure block buffer 103 to the flash memory 101. A comparison may be made between the erasure unit regions into which first and second write data are to be written. The data processing device may further include a write buffer for storing write data.

Abstract: A method of booting up an information processing apparatus is provided. An operating system is divided into a mini operating system (OS) module having a function of bootstrap and an OS main body module having functions other than the function of bootstrap. The mini OS module can be located in a boot block of a boot device, whereas the OS main body module can be located in a file system of the boot device. A firmware or F/W code module stored in a ROM loads the mini OS module into memory when booting up the information processing apparatus. The mini OS module then loads the OS main body module into memory and then initializes the OS main body module.