Patents by Inventor Atsushi Shiraishi
Atsushi Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090019210Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: ApplicationFiled: September 10, 2008Publication date: January 15, 2009Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
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Patent number: 7451266Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.Type: GrantFiled: March 19, 2007Date of Patent: November 11, 2008Assignee: Renesas Technology Corp.Inventors: Chiaki Shinagawa, Atsushi Shiraishi, Motoki Kanamori
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Publication number: 20080257968Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.Type: ApplicationFiled: October 25, 2007Publication date: October 23, 2008Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
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Patent number: 7437602Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: GrantFiled: March 15, 2005Date of Patent: October 14, 2008Assignee: Renesas Technology Corp.Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
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Publication number: 20080229989Abstract: A thread cutting device includes a thread catching member having a catching portion, wherein the thread catching member moves back and forth across a path of a lower thread reeled out from a bobbin so as to catch the lower thread by the catching portion and cuts the lower thread by cooperating with a fixed knife, a first power transmitting portion which transmits a power to the thread catching member, a first cam member provided on a lower shaft rotated by a sewing machine motor and transmits a first moving force to the thread catching member through the first power transmitting portion, a second power transmitting portion which transmits a second moving force from a stepping motor to the thread catching member through the first power transmitting portion.Type: ApplicationFiled: October 2, 2007Publication date: September 25, 2008Inventor: Atsushi Shiraishi
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Patent number: 7402047Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.Type: GrantFiled: June 9, 2006Date of Patent: July 22, 2008Assignees: Renesas Technology Corp., Hitachi UlSI Systems Co., Ltd.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
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Patent number: 7403436Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.Type: GrantFiled: June 16, 2006Date of Patent: July 22, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
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Patent number: 7343445Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.Type: GrantFiled: October 3, 2006Date of Patent: March 11, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
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Publication number: 20080059852Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: ApplicationFiled: October 23, 2007Publication date: March 6, 2008Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Patent number: 7336250Abstract: For statically driving a liquid-crystal optical-modulation device, an alternating electric field produced by a drive signal is applied to a liquid crystal included therein. In a first period in which the alternating electric field has a first polarity, the drive signal is pulse-width modulated based on a first ON-voltage and a first OFF-voltage. In a second period in which the alternating electric field has a second polarity, the drive signal is pulse-width modulated based on a second ON-voltage and a second OFF-voltage.Type: GrantFiled: March 6, 2006Date of Patent: February 26, 2008Assignee: Citizen Holdings Co., Ltd.Inventors: Atsushi Shiraishi, Masafumi Ide
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Patent number: 7330995Abstract: The present invention is directed to suppress data loss caused by power shut-down during a rewriting process and to shorten time required to make a depletion check. A nonvolatile memory apparatus includes a rewritable nonvolatile memory and a card controller. The nonvolatile memory has a physical address area corresponding to a logical address and a save area. In response to a data rewrite instruction on a required logical address, the card controller stores data in a predetermined physical address area corresponding to the logical address to the save area and rewrites the data stored in the physical address area. When rewriting of the physical address area is incomplete, the card controller rewrites the data in the physical address area with the data stored in the save area. Thus, data loss caused by the power shut-down can be suppressed by data backup, and it is sufficient to make the depletion check in two places of the save area and the physical address area.Type: GrantFiled: March 10, 2005Date of Patent: February 12, 2008Assignee: Renesas Technology Corp.Inventors: Atsushi Shiraishi, Atsushi Shikata, Yasuhiro Nakamura, Makoto Obata
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Patent number: 7305589Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: May 8, 2002Date of Patent: December 4, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Patent number: 7303138Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.Type: GrantFiled: March 20, 2006Date of Patent: December 4, 2007Assignee: Renesas Technology Corp.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
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Patent number: 7291019Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.Type: GrantFiled: June 9, 2006Date of Patent: November 6, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
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Patent number: 7291018Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.Type: GrantFiled: June 9, 2006Date of Patent: November 6, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
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Publication number: 20070186033Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.Type: ApplicationFiled: March 19, 2007Publication date: August 9, 2007Inventors: Chiaki Shinagawa, Atsushi Shiraishi, Motoki Kanamori
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Publication number: 20070150649Abstract: A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub memory block within a second memory block in parallel. The first sub memory block has a management area for storing a management information including linking information between the first sub memory block corresponding sub memory blocks of other memory blocks. A control circuit controls reading the linking information from the first sub memory block in accordance with address information, and programming to the first sub memory block in accordance with the address information and corresponding sub memory blocks by the linking information.Type: ApplicationFiled: February 23, 2007Publication date: June 28, 2007Inventors: Shinsuke Asari, Takayuki Tamura, Atsushi Shiraishi
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Patent number: 7234644Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.Type: GrantFiled: March 20, 2006Date of Patent: June 26, 2007Assignee: Renesas Technology Corp.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
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Publication number: 20070111554Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.Type: ApplicationFiled: June 9, 2006Publication date: May 17, 2007Inventors: Hirotaka Nishizaw, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
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Patent number: 7216597Abstract: A threading device for a sewing machine includes a needle bar provided with a guide member having a stopper portion, a threading shaft having a threading member, operation means having a guide groove formed in a spiral shape with respect to a rotating axis of the threading shaft, and a pin, which is fixed to the threading shaft, having both ends protruded outward in a radial direction with respect to the threading shaft. One end of the pin penetrates the guide groove while the other end of the pin engages with the stopper portion. The threading device further includes erroneous rotation preventing means which prevents the threading shaft from rotating in when the threading shaft moves downward, and permits the threading shaft to rotate when the second end of the pin engages with the stopper portion.Type: GrantFiled: May 26, 2006Date of Patent: May 15, 2007Assignee: Juki CorporationInventor: Atsushi Shiraishi