Abstract: A remote control light receiver receives the infrared rays from an infrared LED incorporated in a remote control unit operated by the user, extracts the signal transmitted from the remote control unit, and outputs the extracted signal to a control microcomputer. The carrier frequency of the signal transmitted from the remote control unit is 38 kHz. A PWM control circuit performs PWM control by using an arbitrary PWM frequency within a range of 300 Hz to 3 kHz. By separating the PWM frequency and the frequency (carrier frequency) of the signal for remote control into different bands, the signal for remote control can be restrained from being affected by the turning on of the light source by PWM control, whereby remote control can be prevented from malfunctioning.

Abstract: A remote control light receiver receives the infrared rays from an infrared LED incorporated in a remote control unit operated by the user, extracts the signal transmitted from the remote control unit, and outputs the extracted signal to a control microcomputer. The carrier frequency of the signal transmitted from the remote control unit is 38 kHz. A PWM control circuit performs PWM control by using an arbitrary PWM frequency within a range of 300 Hz to 3 kHz. By separating the PWM frequency and the frequency (carrier frequency) of the signal for remote control into different bands, the signal for remote control can be restrained from being affected by the turning on of the light source by PWM control, whereby remote control can be prevented from malfunctioning.

Abstract: A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.

Abstract: A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.

Abstract: A frequency demodulator of the present invention includes: an amplification section for receiving a frequency-modulated signal and amplifying the frequency-modulated signal based on a gain so as to produce a digital signal having a predetermined level and an inverted signal of the digital signal; a digital demodulation section for receiving the digital signal and frequency-demodulating the digital signal; an amplitude detection section for receiving the digital signal and the inverted signal of the digital signal, and detecting maximum amplitude values of the digital signal and the inverted signal for a predetermined period of time so as to produce an amplitude signal in proportion to the maximum values; and a gain controlling section for varying the gain based on the amplitude signal.

Abstract: A delta sigma modulator includes, an addition circuit with 4 switches, an integration circuit, an analog-digital conversion circuit, a delay circuit, and a digital-analog conversion circuit with 2 capacitors and 6 switches. The addition circuit adds an input signal and a feedback signal, the integration circuit integrates the output of the addition circuit, the analog-digital conversion circuit converts the output of the integration circuit into a digital signal, and the delay circuit delays the output digital signal of the analog-digital conversion circuit.