Patents by Inventor Atsushi Tsuboi
Atsushi Tsuboi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117984Abstract: Provided is an air conditioner including an indoor unit provided with a microphone element for receiving voice instructions, such that a voice instruction spoken by an operator is acquired with high quality and control based on the voice instruction spoken by the operator is likely to be ensured. The air conditioner includes an indoor unit, a transmission unit, and a reception unit. The indoor unit has a main body and a microphone element. The main body has formed therein a blow-out port through which air-conditioned air is blown out toward a space to be air-conditioned. The microphone element accepts a voice instruction captured from a voice capturing portion arranged at a position that deviates from a ventilation space through which the air blown out from the blow-out port flows, in such a manner as to face the space to be air-conditioned. The transmission unit transmits the voice instruction accepted by the microphone element to an outside as a signal.Type: ApplicationFiled: December 15, 2023Publication date: April 11, 2024Inventors: Kousuke TSUBOI, Takao SONODA, Makoto IKEDA, Tetsushi TSUDA, Yu OTA, Yuuichi KITA, Kenji AMANO, Atsushi MATSUBARA, Tomomi KUKITA, Naoko KURIYAMA, Tomoyoshi ASHIKAGA, Gen KUMAMOTO
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Patent number: 11818339Abstract: In a case where it is identified based on fisheye information that an input image is a fisheye image, a block position computing section computes the position of a processing target block relative to a fisheye center, and outputs, to a table selecting section, positional information representing the computed position. In a case where it is identified based on fisheye information that an input image is a fisheye image, the table selecting section selects, on the basis of positional information, an intra-prediction mode table according to the position of a processing target block from a plurality of intra-prediction mode tables, and outputs the selected intra-prediction mode table to a prediction image generating section.Type: GrantFiled: April 3, 2019Date of Patent: November 14, 2023Assignee: SONY CORPORATIONInventors: Junichi Matsumoto, Atsushi Tsuboi, Hiromichi Ueno
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Patent number: 11605712Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.Type: GrantFiled: May 25, 2021Date of Patent: March 14, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Shimpei Yamaguchi, Atsushi Tsuboi, Atsushi Endo, Masaru Sugimoto, Hiroshi Yano, Yasushi Kodashima, Masanobu Igeta
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Publication number: 20220199463Abstract: A method of manufacturing a semiconductor device includes: forming a first film containing carbon over a silicon nitride film and a first conductive film; forming a first silicon oxide film surrounding the first film over the silicon nitride film and the first conductive film; removing the first film to form, in the first silicon oxide film, a first opening that exposes at least a part of the silicon nitride film and at least a part of the first conductive film; and forming a second conductive film on and in contact with the first conductive film in the first opening.Type: ApplicationFiled: March 15, 2022Publication date: June 23, 2022Inventors: Shimpei YAMAGUCHI, Kiyotaka IMAI, Atsushi TSUBOI
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Publication number: 20210376123Abstract: A method including depositing a dielectric film on a substrate including stacked structures with recessed portions formed on side surfaces of each of the stacked structures, wherein the dielectric film is deposited so that the stacked structures are covered at a thickness which is equal to or less than half a width of the recessed portions; filling a trench or trenches that are located between the stacked structures with a sacrificial film; etching the sacrificial film along the stacked structures; etching the dielectric film so that the dielectric film is etched more than the sacrificial film; removing the sacrificial film; after the removing of the sacrificial film, depositing a dielectric film to a thickness equal to or less than half the width of the recessed portions; and etching the deposited dielectric film, on a condition that the deposited dielectric film remains in the recessed portions.Type: ApplicationFiled: May 25, 2021Publication date: December 2, 2021Applicant: Tokyo Electron LimitedInventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masanobu IGETA, Masaru SUGIMOTO, Luis FERNANDEZ
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Publication number: 20210375684Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.Type: ApplicationFiled: May 25, 2021Publication date: December 2, 2021Applicant: Tokyo Electron LimitedInventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masaru SUGIMOTO, Hiroshi YANO, Yasushi KODASHIMA, Masanobu IGETA
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Publication number: 20210168363Abstract: In a case where it is identified based on fisheye information that an input image is a fisheye image, a block position computing section computes the position of a processing target block relative to a fisheye center, and outputs, to a table selecting section, positional information representing the computed position. In a case where it is identified based on fisheye information that an input image is a fisheye image, the table selecting section selects, on the basis of positional information, an intra-prediction mode table according to the position of a processing target block from a plurality of intra-prediction mode tables, and outputs the selected intra-prediction mode table to a prediction image generating section.Type: ApplicationFiled: April 3, 2019Publication date: June 3, 2021Applicant: SONY CORPORATIONInventors: Junichi MATSUMOTO, Atsushi TSUBOI, Hiromichi UENO
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Patent number: 10461159Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.Type: GrantFiled: April 30, 2018Date of Patent: October 29, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hironobu Miyamoto, Tatsuo Nakayawa, Yasuhiro Okamoto, Atsushi Tsuboi
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Patent number: 10249715Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.Type: GrantFiled: May 25, 2017Date of Patent: April 2, 2019Assignee: Renesas Electronics CorporationInventors: Hironobu Miyamoto, Tatsuo Nakayama, Atsushi Tsuboi, Yasuhiro Okamoto, Hiroshi Kawaguchi
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Publication number: 20180342589Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.Type: ApplicationFiled: April 30, 2018Publication date: November 29, 2018Applicant: Renesas Electronics CorporationInventors: Hironobu MIYAMOTO, Tatsuo NAKAYAWA, Yasuhiro OKAMOTO, Atsushi TSUBOI
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Publication number: 20180026099Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.Type: ApplicationFiled: May 25, 2017Publication date: January 25, 2018Applicant: Renesas Electronics CorporationInventors: Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Atsushi TSUBOI, Yasuhiro OKAMOTO, Hiroshi KAWAGUCHI
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Patent number: 8934767Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.Type: GrantFiled: October 23, 2013Date of Patent: January 13, 2015Assignee: Sony CorporationInventors: Ryoichi Nakashima, Atsushi Tsuboi
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Publication number: 20140050467Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.Type: ApplicationFiled: October 23, 2013Publication date: February 20, 2014Applicant: Sony CorporationInventors: Ryoichi NAKASHIMA, Atsushi TSUBOI
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Patent number: 8577219Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.Type: GrantFiled: November 2, 2011Date of Patent: November 5, 2013Assignee: Sony CorporationInventors: Ryoichi Nakashima, Atsushi Tsuboi
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Publication number: 20120155849Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.Type: ApplicationFiled: November 2, 2011Publication date: June 21, 2012Applicant: SONY CORPORATIONInventors: Ryoichi NAKASHIMA, Atsushi Tsuboi
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Patent number: 7280008Abstract: In a fitting region for a SAW filter which includes langasite as its piezoelectric element, there are included an input side terminal electrode and an output side terminal electrode which are connected to an input terminal and to an output terminal of the SAW filter. To each of the terminal electrodes, at a position which is separated by just a predetermined distance from the fitting region of the SAW filter, there is connected a micro strip line which extends in mutually opposite directions along a direction which is parallel to the transmission direction of a frequency signal within the SAW filter. A slit is provided in the fitting region of the SAW filter and extends in a direction which intersects the transmission direction of the frequency signal within the SAW filter. A plurality of through holes are provided in the printed substrate and electrically connect together its surface and its rear surface which is grounded.Type: GrantFiled: January 23, 2003Date of Patent: October 9, 2007Assignees: Mitsubishi Materials Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kunio Yamaguchi, Ryouhei Kimura, Atsushi Tsuboi, Kenyu Morozumi
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Publication number: 20030104686Abstract: In a semiconductor device that includes a barrier film, an electrode pad on the barrier film, and a solder ball in the electrode pad, the electrode pad is prevented from exfoliating from the barrier film by a side wall film separating the solder ball from a boundary between the barrier film and the electrode pad.Type: ApplicationFiled: November 15, 2002Publication date: June 5, 2003Applicant: NEC CORPORATIONInventor: Atsushi Tsuboi
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Patent number: 6528881Abstract: In a semiconductor device that includes a barrier film, an electrode pad on the barrier film, and a solder ball on the electrode pad, the electrode pad is prevented from exfoliating from the barrier film by a side wall film separating the solder ball from a boundary between the barrier film and the electrode pad.Type: GrantFiled: August 17, 2000Date of Patent: March 4, 2003Assignee: NEC CorporationInventor: Atsushi Tsuboi
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Patent number: 6413841Abstract: First, a polysilicon film is formed on a gate oxide film. Next, a polysilicon oxide film is formed on the polysilicon film. Thereafter, the polysilicon film is thermally treated to allow a crystal grain in the polysilicon film to grow from the gate oxide film and the polysilicon oxide film. In a MOS type semiconductor device manufactured in this manner has a gate electrode formed of a plurality of laminated polycrystalline silicon layers each having substantially a single crystal grain in a thickness direction of the gate electrode.Type: GrantFiled: October 21, 1999Date of Patent: July 2, 2002Assignee: NEC CorporationInventor: Atsushi Tsuboi
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Publication number: 20020043124Abstract: A plastic gear is provided which includes a main body portion and a toothed portion. The main body portion is made of a synthetic resin containing reinforcement fibers. The toothed portion is made of a synthetic resin which is the same as the synthetic resin of which the main body portion is made except that it does not contain any reinforcement fibers. A method of producing such a plastic gear is also provided.Type: ApplicationFiled: April 13, 2001Publication date: April 18, 2002Applicant: UNISIA JECS CORPORATIONInventors: Hirotaka Shiga, Atsushi Tsuboi, Yuzuru Morioka