Abstract: A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.

Abstract: The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

Abstract: A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.

Abstract: The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

Abstract: A method correlates a timing target for electronic design automation (EDA) design tools by comparing slack distributions. A method of designing an integrated circuit can include designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization and placement of cells with embedded timing analysis and optimization. The method can also include designing an integrated circuit by routing with embedded timing analysis and optimization; performing reference timing analysis; performing reference timing analysis and embedded timing analysis using a parasitic estimation model. The method can also include comparing at least two slack distributions resulting from timing analyses. The method can include calculating and comparing autocorrelation functions of slack distributions. The method can include calculating interrcorrelation functions of slack distributions. An embodiment teaches an integrated circuit designed by the method taught.