Abstract: A GaAs (gallium arsenide) semiconductor memory device includes a plurality of memory cells connected in a matrix form by employing a plurality of bit lines and of word lines, and of word line drivers. The memory device is operable under a single power supply. Transfer gates of the memory cells are normally-on type GaAs metal-semiconductor field effect transistors (MESFET's). A parallel circuit including a Schottky diode and a switching GaAs-MESFET is interposed between commonly-connected sources of driver MESFET's of each of the memory cells and the ground line, so that a higher potential of the commonly-connected sources is clamped due to the clamping effect of the Schottky diode when the switching GaAs-MESFET is turned off.

Abstract: A gallium arsenide NAND gate is connected between a power source and a ground potential. The gate is comprised of a load transistor of a normally-on type field effect transistor having an output terminal and a drain connected to the power source, a first driver transistor of a normally-off type field effect transistor having a gate electrode as a first input terminal and a source-to-drain current path series-connected to that of the load transistor, and a second driver transistor of two normally-off type field effect transistors having a common gate electrode for a second input terminal and source-to-drain current paths series-connected between the power source and the ground potential through the series-connected first driver transistor and load transistor. The normally-off type field effect transistors are parallel-connected to each other so as to equally constitute a single driver transistor as the second driver transistor.