Patents by Inventor Atuyuki Yosimoto

Atuyuki Yosimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data transfer apparatus and method
    Patent number: 6954806
    Abstract: A data transfer apparatus and method that can make efficient use of a memory and a common bus by controlling a DMA controller through descriptor control, and can thereby achieve a data transfer with increased communication processing speed. The data transfer apparatus, which executes a DMA transfer by controlling the DMA controller through the use of a descriptor, includes: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: October 11, 2005
    Assignee: Fujitsu Limited
    Inventors: Atuyuki Yosimoto, Kazumi Hayasaka, Hiroshi Saito, Yoshimasa Suetsugu
  • Data transfer apparatus and method
    Publication number: 20030188054
    Abstract: A data transfer apparatus and method that can make efficient use of a memory and a common bus by controlling a DMA controller through descriptor control, and can thereby achieve a data transfer with increased communication processing speed. The data transfer apparatus, which executes a DMA transfer by controlling the DMA controller through the use of a descriptor, includes: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.
    Type: Application
    Filed: March 28, 2003
    Publication date: October 2, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Atuyuki Yosimoto, Kazumi Hayasaka, Hiroshi Saito, Yoshimasa Suetsugu