Abstract: A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register.

Abstract: A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register.

Abstract: A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence.

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.

Abstract: A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

Abstract: In accordance with the present invention, a resource allocation array has at least one resource input line (Aj), at least one request for resource input line (Ri) and at least one cell (12) coupled to the at least one resource input line and to the at least one request for resource line. The resource allocation array assigns one resource to one request for the resource. The one resource and the one request for the resource are both of a group of at least one resource and of a group of at least one request for the resource, respectively. The availability and unavailability of the resource is represented by a first and a second predetermined resource signal, respectively. The assertion and non assertion of the request for resource is represented by a third and a fourth predetermined request for resource signal, respectively. The at least one resource input line is associated with one of the at least one resource signals.