Patents by Inventor Augustin Jinwoo Hong
Augustin Jinwoo Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574912Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: GrantFiled: December 4, 2020Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
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Publication number: 20210091086Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo HONG, Young-Ju LEE, Joon-Yong CHOE, Jung-hyun KIM, Sang-jun LEE, Hyeon-Kyu LEE, Yoon-Chul CHO, Je-Min PARK, Hyo-Dong BAN
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Patent number: 10886277Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: GrantFiled: August 21, 2018Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
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Patent number: 10522550Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.Type: GrantFiled: November 8, 2018Date of Patent: December 31, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
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Patent number: 10332831Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.Type: GrantFiled: June 30, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Augustin Jinwoo Hong, Dae-Ik Kim, Chan-Sic Yoon, Ki-Seok Lee, Dong-Min Han, Sung-Ho Jang, Yoo-Sang Hwang, Bong-Soo Kim, Je-Min Park
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Publication number: 20190139963Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: ApplicationFiled: August 21, 2018Publication date: May 9, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo HONG, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
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Publication number: 20190088659Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.Type: ApplicationFiled: November 8, 2018Publication date: March 21, 2019Inventors: Ki Seok LEE, Jeong Seop SHIM, Mi Na LEE, Augustin Jinwoo HONG, Je Min PARK, Hye Jin SEONG, Seung Min OH, Do Yeong LEE, Ji Seung LEE, Jin Seong LEE
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Patent number: 10141316Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.Type: GrantFiled: September 26, 2016Date of Patent: November 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
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Publication number: 20180158773Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.Type: ApplicationFiled: June 30, 2017Publication date: June 7, 2018Inventors: AUGUSTIN JINWOO HONG, DAE-IK KIM, CHAN-SIC YOON, Kl-SEOK LEE, DONG-MIN HAN, SUNG-HO JANG, YOO-SANG HWANG, BONG-SOO KIM, JE-MIN PARK
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Patent number: 9899487Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.Type: GrantFiled: January 12, 2017Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong Lee, Hye-Young Kang, Young-Sin Kim, Yong-Kwan Kim, Byoung-Wook Jang, Augustin Jinwoo Hong, Dong-Sik Kong, Chang-Hyun Cho
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Publication number: 20170263723Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.Type: ApplicationFiled: January 12, 2017Publication date: September 14, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong LEE, Hye-Young Kang, Young-Sin Kim, Yong-Kwan Kim, Byoung-Wook Jang, Augustin Jinwoo Hong, Dong-Sik Kong, Chang-Hyun Cho
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Publication number: 20170200725Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.Type: ApplicationFiled: September 26, 2016Publication date: July 13, 2017Inventors: Ki Seok LEE, Jeong Seop SHIM, Mi Na LEE, Augustin Jinwoo HONG, Je Min PARK, Hye Jin SEONG, Seung Min OH, Do Yeong LEE, Ji Seung LEE, Jin Seong LEE
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Patent number: 9048329Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: GrantFiled: September 12, 2013Date of Patent: June 2, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Patent number: 8664707Abstract: Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.Type: GrantFiled: March 23, 2012Date of Patent: March 4, 2014Assignees: Samsung Electronics Co., Ltd., The Regents of the University of CaliforniaInventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20140015032Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Patent number: 8541832Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: GrantFiled: June 16, 2010Date of Patent: September 24, 2013Assignees: Samsung Electronics Co., Ltd., The Regents of the University of CaliforniaInventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20120181593Abstract: Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Patent number: 8164134Abstract: Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.Type: GrantFiled: June 9, 2009Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20110018051Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: ApplicationFiled: June 16, 2010Publication date: January 27, 2011Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20100308391Abstract: Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.Type: ApplicationFiled: June 9, 2009Publication date: December 9, 2010Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong