Patents by Inventor Augusto Gutierrez
Augusto Gutierrez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230414543Abstract: The present invention pertains to the field of maximizing performance of animals, particularly of gestating or lactating animals and their offspring, particularly of gestating or lactating sows and their offspring. Particularly the present invention is in the field of increasing colostrum production, milk production, colostral- and/or milk protein yield, colostral and/or milk total solids yield, said total solids being the total of fat, protein and lactose, in colostrum and/or milk, colostral- and/or milk lactose yield, and average daily gain of the offspring, improving survival of the offspring and increasing number of offspring at weaning.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Pieter LANGENDIJK, John Henry DOELMAN, Néstor Augusto GUTIÉRREZ CÉSPEDES
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Publication number: 20090065811Abstract: A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped semiconductor contact layer, forming an adhesive contact portion over the platinum contact portion, forming a barrier contact portion over the adhesive contact portion, and forming a gold contact portion over the barrier contact portion. The method further comprises annealing the semiconductor structure to alloy the platinum contact portion with the N-type doped semiconductor contact layer to form a platinum/semiconductor alloyed diffusion contact barrier substantially disposed within the N-type doped semiconductor contact layer.Type: ApplicationFiled: September 7, 2007Publication date: March 12, 2009Inventors: Ping-Chih Chang, Xiaobing Mei, Augusto Gutierrez-Aitken
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Publication number: 20090045437Abstract: The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure.Type: ApplicationFiled: August 15, 2007Publication date: February 19, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Rajinder Sandhu, Abdullah Cavus, Cedric Monier, Augusto Gutierrez
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Publication number: 20080251891Abstract: The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Inventors: Yeong-Chang Chou, Peter S. Nam, Chun H. Lin, Augusto Gutierrez, Jeffrey Ming-Jer Yang, Michael Wojtowicz
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Publication number: 20080230803Abstract: A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 ?. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 ?, and a concentration of indium of about 86% at a top of the combined layer.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Cedric Monier, Randy Sandhu, Abdullah Cavus, Augusto Gutierrez-Aitken
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Publication number: 20070215280Abstract: A semiconductor surface processing method in one example comprises disposing a polishing pad in rotating engagement with a semiconductor wafer to be polished, dripping a first polishing solution onto the polishing pad at a first drip rate, and, concurrently, dripping a second polishing solution onto the polishing pad at a second drip rate.Type: ApplicationFiled: March 15, 2006Publication date: September 20, 2007Inventors: Rajinder Sandhu, Roosevelt Johnson, Cedric Monier, Augusto Gutierrez-Aitken
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Publication number: 20050184312Abstract: A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.Type: ApplicationFiled: April 28, 2005Publication date: August 25, 2005Inventors: Donald Sawdai, Gregory Leslie, Augusto Gutierrez-Aitken
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Patent number: 6924203Abstract: A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.Type: GrantFiled: May 27, 2003Date of Patent: August 2, 2005Assignee: Northrop Grumman CorporationInventors: Donald James Sawdai, Gregory Scott Leslie, Augusto Gutierrez-Aitken
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Publication number: 20040238843Abstract: A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.Type: ApplicationFiled: May 27, 2003Publication date: December 2, 2004Inventors: Donald James Sawdai, Gregory Scott Leslie, Augusto Gutierrez-Aitken
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Patent number: 6566724Abstract: A low dark current photodiode and a method for reducing dark current in a photodiode. A preferred embodiment of the present invention provides a photodiode comprising a barrier layer. The barrier layer comprises a barrier layer material having a wider band-gap than the band-gap of the absorption layer material of the photodiode. The barrier layer comprises sublayers, which are doped to position the high-electric field region at the pn junction of the photodiode in the barrier layer. The method for reducing dark current in a photodiode comprises building a barrier layer into the structure of a photodiode. Building the barrier layer comprises building a layer of semiconductor material with wider band-gap than the i-layer material. Building the barrier layer preferably further comprises doping the barrier layer material to position the high-energy region at the pn junction of the photodiode in the barrier layer, thus reducing dark current.Type: GrantFiled: December 19, 2000Date of Patent: May 20, 2003Assignee: Northrop Grumman CorporationInventors: Augusto Gutierrez-Aitken, Edward A. Rezek
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Publication number: 20030089958Abstract: A low dark current photodiode and a method for reducing dark current in a photodiode. A preferred embodiment of the present invention provides a photodiode comprising a barrier layer. The barrier layer comprises a barrier layer material having a wider band-gap than the band-gap of the absorption layer material of the photodiode. The barrier layer comprises sublayers, which are doped to position the high-electric field region at the pn junction of the photodiode in the barrier layer. The method for reducing dark current in a photodiode comprises building a barrier layer into the structure of a photodiode. Building the barrier layer comprises building a layer of semiconductor material with wider band-gap than the i-layer material. Building the barrier layer preferably further comprises doping the barrier layer material to position the high-energy region at the pn junction of the photodiode in the barrier layer, thus reducing dark current.Type: ApplicationFiled: December 19, 2000Publication date: May 15, 2003Inventors: Augusto Gutierrez-Aitken, Edward A. Rezek
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Patent number: 5679478Abstract: A reserve, energy sourced, or deferred action battery in which each battery cell is provided a separate reservoir containing the necessary electrolyte fluid for that cell. A simple design is then possible as the electrolyte fluid is stored in close proximity to the battery cells when needed at the time of activating the battery. A combination of two electrolyte fluids may be used that react exothermically when mixed together at the time of activation thereby producing heat. The production of heat allows the battery to activate at existing cold ambient temperatures that would otherwise render the reserve battery without sufficient operating power. The invention also provides an activation system which ensures reliable activation of the battery and ensures that the battery is not is subject to unintended activation.Type: GrantFiled: February 13, 1996Date of Patent: October 21, 1997Assignee: Reserve Battery Cell, L.P.Inventors: Keith Alan Hancock, Thomas Augusto Gutierrez, Jeffrey Michael Kalman, Nicholas Emile Stanca
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Patent number: 5668461Abstract: An electronic control system for a reserve, energy sourced, or deferred action battery that determines start-up temperature and voltage conditions to determine the necessary amount of charge to deliver from a reserve battery to a discharged battery. A temperature sensor is used to measure the ambient temperature and operating temperature of the electronic control system. A target charge value is selected based on the ambient temperature and startup voltage information. The operating temperature of the electronics control system is monitored to ensure the most efficient and reliable delivery of charge. Indications are provided to the user to provide information regarding charging status, connection status, and voltage levels.Type: GrantFiled: February 13, 1996Date of Patent: September 16, 1997Assignee: Reserve Battery Cell, L.P.Inventors: Keith Alan Hancock, Joseph Thomas Scopaz, Gerald Lewis, Thomas Augusto Gutierrez
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Patent number: 4396144Abstract: A telescoped container for storage and transporting of foodstuffs comprising an opened top container body with an integral liner and a separate container cover telescopically disposed on the container body. The integral liner consists of four liner panels which are reversely folded to lie in face-to-face relationship with the outer surfaces of the sidewalls of the container body to form an outer perimetrical reinforcement.Type: GrantFiled: April 22, 1982Date of Patent: August 2, 1983Assignee: Container Corporation of AmericaInventors: Augusto Gutierrez, Edgar Londono