Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Abstract: Second machine learning models trained using respective second data sets can be received. The second machine learning models can be run using a first data set used in training a first machine learning model, where the second machine learning models produce respective outputs. Scores associated with the second machine learning models can be determined by comparing the respective outputs with ground truth associated with the first data set. Based on the scores associated with the second machine learning models, whether the first data set is to be discarded or kept can be determined for training the first machine learning model.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.

Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.

Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Abstract: Embodiments relate to an input-encoding technique in conjunction with federation. Participating entities are arranged in a collaborative relationship. Each participating entity trains a machine learning model with an encoder on a training data set. The performance of each of the models is measured and at least one of the models is selectively identified based on the measured performance. An encoder of the selectively identified machine learning model is shared with each of the participating entities. The shared encoder is configured to be applied by the participating entities to train the first and second machine learning models, which are configured to be merged and shared in the federated learning environment.

Abstract: A method, computer program product, and/or system associates a number of tokens with a plurality of frequency domains (for example, cores) of a central processing unit (CPU) computer chip. The number of tokens allotted to the CPU is based on the CPU power budget. Cores are organized as a ring topology. A token pool traverses the ring, picks up excess tokens from cores having excess tokens, and gives the tokens to cores that need additional tokens. Tokens acquired by a core allows the core to increase operating frequency by an increment represented by the tokens. Consequently, power usage is weighted toward heavily loaded cores and away from lightly loaded cores. Overall power usage of the CPU remains within a power budget. The method budgets power optimally to sustain turbo frequencies for longer durations by not allowing control units to increase frequency in absence of any useful high frequency benefiting workload.

Abstract: A method, computer program product, and/or system associates a number of tokens with a plurality of frequency domains (for example, cores) of a central processing unit (CPU) computer chip. The number of tokens allotted to the CPU is based on the CPU power budget. Cores are organized as a ring topology. A token pool traverses the ring, picks up excess tokens from cores having excess tokens, and gives the tokens to cores that need additional tokens. Tokens acquired by a core allows the core to increase operating frequency by an increment represented by the tokens. Consequently, power usage is weighted toward heavily loaded cores and away from lightly loaded cores. Overall power usage of the CPU remains within a power budget. The method budgets power optimally to sustain turbo frequencies for longer durations by not allowing control units to increase frequency in absence of any useful high frequency benefiting workload.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: A computer system that has two or more processing engines (PE), each capable of performing one or more operations on one or more operands but one or more of the PEs performs the operations unreliably. Initial results of each operation are debiased to create a debiased result used by the system instead of the initial result. The debiased result has an expected value equal to a correct output where the correct output is the initial result the respective operation would have produced if the respective operation performed was reliable.

Abstract: Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.

Abstract: A computer system that has two or more processing engines (PE), each capable of performing one or more operations on one or more operands but one or more of the PEs performs the operations unreliably. Initial results of each operation are debiased to create a debiased result used by the system instead of the initial result. The debiased result has an expected value equal to a correct output where the correct output is the initial result the respective operation would have produced if the respective operation performed was reliable.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.

Abstract: In a first device in response to an event input, using a processor and a memory, a local classification and a local classification confidence score corresponding to the event input are computed. At the first device in response to a broadcast request, a remote classification and a remote classification confidence score corresponding to the event input are received, the remote classification and the remote classification confidence score being computed at a second device. At the first device, a consensus classification including the most frequent classification from a set of all received remote classifications and the local classification is formed, provided the number of classifications including the most frequent classification exceeds a threshold. In response to a consensus classification confidence score corresponding to the consensus classification exceeding a confidence threshold, a local classification model is updated.

Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.