Abstract: A semiconductor memory or storage circuit includes cross coupled transistors and isolating transistors operating at a first threshold voltage and load transistors for the cross coupled transistors operating at a second threshold voltage. The storage cell is disposed in a matrix of word and bit lines. The load devices are connected between a supply voltage and the cross coupled transistors which are returned to a reference potential. The isolating transistors are connected between the cross coupled transistors and adjacent bit lines. The word line is connected to the gates of both the isolating transistors and the load devices. When the word line is down, the isolating transistors are turned off and the load devices supply sufficient current to retain the stored information in the cross coupled transistors. When the word line is raised, the gate voltage of the load transistors is raised to supply additional current to the circuit.