Patents by Inventor Austen J. Hypher

Austen J. Hypher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Termination impedance apparatus with calibration circuit and method therefor
    Patent number: 8963577
    Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Warren R. Anderson, Shyam S. Sivakumar, Austen J. Hypher
  • TERMINATION IMPEDANCE APPARATUS WITH CALIBRATION CIRCUIT AND METHOD THEREFOR
    Publication number: 20140325135
    Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 30, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Warren R. Anderson, Shyam S. Sivakumar, Austen J. Hypher
  • Memory request reordering in a data processing system
    Patent number: 6976135
    Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: December 13, 2005
    Assignee: Magnachip Semiconductor
    Inventors: Gerry R. Talbot, Austen J. Hypher
  • Memory request reordering in a data processing system
    Patent number: 6272600
    Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: August 7, 2001
    Assignee: Hyundai Electronics America
    Inventors: Gerry R. Talbot, Austen J. Hypher