Patents by Inventor Austin H. Roach

Austin H. Roach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10833658
    Abstract: Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 10, 2020
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew J Kay, Adam Duncan, Matthew Gadlage, Austin H Roach, Glenn Berger
  • Publication number: 20170103818
    Abstract: Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.
    Type: Application
    Filed: July 11, 2016
    Publication date: April 13, 2017
    Inventors: Austin H. Roach, Matthew Gadlage, Adam Duncan, James David Ingalls, Matthew Kay
  • Patent number: 9620242
    Abstract: Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 11, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Austin H. Roach, Matthew Gadlage, Adam Duncan, James David Ingalls, Matthew Kay