Patents by Inventor Austin Roach

Austin Roach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190222202
    Abstract: Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 18, 2019
    Inventors: Matthew Kay, Adam Duncan, Matthew Gadlage, Austin Roach, Glenn Burger
  • Patent number: 10204875
    Abstract: Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons, and ions to create catastrophic failures in integrated circuits. Exemplary systems include latch-up circuits with floating gate bit cells which, when triggered, close the latch-up circuits so that the latch-up circuits can amplify current in a positive feedback loop to create a short circuit to inhibit unauthorized individuals from probing or modifying an integrated circuit.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 12, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew Kay, Matthew Gadlage, Adam Duncan, Brett Hamilton, Brett Werner, Austin Roach
  • Publication number: 20180301427
    Abstract: Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons, and ions to create catastrophic failures in integrated circuits. Exemplary systems include latch-up circuits with floating gate bit cells which, when triggered, close the latch-up circuits so that the latch-up circuits can amplify current in a positive feedback loop to create a short circuit to inhibit unauthorized individuals from probing or modifying an integrated circuit.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 18, 2018
    Applicant: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew Kay, Matthew Gadlage, Adam Duncan, Brett Hamilton, Brett Werner, Austin Roach
  • Patent number: 9685231
    Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 20, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
  • Patent number: 9601201
    Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: March 21, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
  • Patent number: 9425803
    Abstract: Methods and apparatuses for implementing a Physically Unclonable Function (PUF) and random number generator capabilities comprising providing a device under test comprising a plurality of bits comprising integrated circuits each including a capacitor; placing the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; reading all bits and recording addresses of bits that have experienced bit flip from a first state to a second state comprising from “1” to “0” state; performing selecting a plurality of said recorded addresses to generate a PUF or cryptographic key; and performing an operation comprising a test or verification operation with said generated information PUF or key. Various hardware elements are also provided as well as machine readable instructions for implementing and controlling aspects of the invention.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 23, 2016
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Adam Duncan, Matthew Gadlage, Austin Roach, Matthew Kay
  • Publication number: 20160211021
    Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
  • Publication number: 20150144695
    Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.
    Type: Application
    Filed: April 7, 2014
    Publication date: May 28, 2015
    Applicant: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
  • Patent number: D818327
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: May 22, 2018
    Inventor: Brad Austin Roach