Patents by Inventor Avadhani Shridhar

Avadhani Shridhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921649
    Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Tiruvur Radhakrishna Ramesh, Avadhani Shridhar, Senthilkumar Diraviam, Gary Lin
  • Publication number: 20230305752
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
  • Patent number: 11704061
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
  • Patent number: 11662942
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device specifying a subset of n buffers of the plurality of buffers in which to transfer a data payload relating to the command.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventors: Avadhani Shridhar, Neil Buxton, Steven Wells, Nicole Ross
  • Publication number: 20230153024
    Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Applicant: Kioxia Corporation
    Inventors: Avadhani SHRIDHAR, Neil BUXTON
  • Patent number: 11556272
    Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 17, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Avadhani Shridhar, Neil Buxton
  • Publication number: 20220300199
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
  • Publication number: 20220300194
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device specifying a subset of n buffers of the plurality of buffers in which to transfer a data payload relating to the command.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Avadhani Shridhar, Neil Buxton, Steven Wells, Nicole Ross
  • Publication number: 20220091775
    Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Avadhani SHRIDHAR, Neil BUXTON
  • Publication number: 20170279489
    Abstract: Techniques for processing, storing, and using vectoring coefficients in a wireline communication system are disclosed. A wireline device selects victim-disturber specific parameters corresponding to a pair of digital subscriber line (DSL) lines and a subset of tones used to communicate data over the pair of DSL lines and downsamples, based at least in part on a downsampling parameter of the victim-disturber specific parameters, a set of vectoring coefficients. Each set of vectoring coefficients is quantized, and then a set of change values for each set of downsampled and quantized vectoring coefficients is compressed. The set of change values represent a difference between the downsampled and quantized vectoring coefficients across the subset of tones. The wireline device uses the compressed sets of change values to perform vectoring over the DSL lines.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 28, 2017
    Inventors: Shailendra Kumar Singh, Amitkumar Mahadevan, Laurent Francis Alloin, Avadhani Shridhar
  • Publication number: 20170006154
    Abstract: Methods, systems, and devices are described for wired communication. A first distribution point uses sets of modems to communicate with a second distribution point over a crosstalk link to exchange information and coordinate the use of multiple sets of frequency bands. In some cases, the first distribution point may share a cable binder with the second distribution point and detect crosstalk on the subscriber lines in the cable binder. Based at least in part on the crosstalk detected by the first distribution point, the first and second distribution points may communicate over a crosstalk link between sets of lines in the binder. The distribution points may use one or more sets of predefined tones within the multiple sets of frequency bands to exchange messages, where the messages may include synchronization information, operating parameters, or control and data information.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 5, 2017
    Inventors: Avadhani Shridhar, Shailendra Kumar Singh, William Edward Keasler, JR., Debajyoti Pal
  • Patent number: 9509518
    Abstract: In general, the present invention provides an efficient usage of Far End Crosstalk (FEXT) coefficient memory in a G.fast vectoring system. According to certain aspects, embodiments of the invention provide a simple scheme for efficient management of the Discontinuous (DO) and Regular Operation (RO) FEXT coefficient memories to handle the complexity of lines joining/leaving the system in both regular and DO groups. In embodiments, by disabling the power-efficient, Discontinuous Operation, a G.fast system according to the invention first frees up the DO coefficient memory. Next, the system uses this memory as the staging area to manage joining/leaving events. Finally the system re-enables to the power-efficient Discontinuous Operation and re-populates the DO coefficient memory.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: November 29, 2016
    Assignee: Ikanos Communications, Inc.
    Inventors: Murli Mohan Rao, Kevin D. Fisher, Laurent Francis Alloin, Avadhani Shridhar
  • Publication number: 20150341180
    Abstract: In general, the present invention provides an efficient usage of Far End Crosstalk (FEXT) coefficient memory in a G.fast vectoring system. According to certain aspects, embodiments of the invention provide a simple scheme for efficient management of the Discontinuous (DO) and Regular Operation (RO) FEXT coefficient memories to handle the complexity of lines joining/leaving the system in both regular and DO groups. In embodiments, by disabling the power-efficient, Discontinuous Operation, a G.fast system according to the invention first frees up the DO coefficient memory. Next, the system uses this memory as the staging area to manage joining/leaving events. Finally the system re-enables to the power-efficient Discontinuous Operation and re-populates the DO coefficient memory.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 26, 2015
    Inventors: Murli Mohan RAO, Kevin D. FISHER, Laurent Francis ALLOIN, Avadhani SHRIDHAR
  • Publication number: 20150270942
    Abstract: According to certain general aspects, the present invention relates to methods for transmitting signals on twisted wire-pairs above 30 MHz using frequency division duplexing (FDD) in support of 1 Gb/s aggregate services on short loop lengths while maintaining spectral compatibility with legacy ADSL2 (?2.2 MHz bandwidth) and VDSL2 services (?30 MHz bandwidth). An advantage of the FDD approach for Gb/s transmission according to the invention is spectral compatibility with legacy DSL services without the sacrifice of any capacity of the wider band.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 24, 2015
    Inventors: Massimo SORBARA, Julien Daniel PONS, Avadhani SHRIDHAR, Debajyoti PAL
  • Patent number: 9065534
    Abstract: A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: June 23, 2015
    Assignee: IKANOS COMMUNICATIONS, INC.
    Inventors: Avadhani Shridhar, Kevin Fisher
  • Publication number: 20150124948
    Abstract: According to certain aspects, the present invention provides methods and apparatuses for managing a low power mode in xDSL systems, and more particularly directed to a L2 mode exit procedure for VDSL systems that is robust and quick. In embodiments, parameters for exiting a low power mode are communicated between upstream and downstream modems before the low power mode is entered. According to certain aspects, these parameters include configurations for incrementally exiting low power mode in a plurality of stages. Embodiments of the invention include quickly estimating SNR at one or more stages of this plurality of stages. Additional or alternative embodiments include reliably signaling the beginning of low power mode exit. According to certain aspects, such signaling can include a synchro sequence of inverted and normal sync symbols.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Avadhani SHRIDHAR, Massimo SORBARA
  • Publication number: 20130051488
    Abstract: A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.
    Type: Application
    Filed: February 23, 2012
    Publication date: February 28, 2013
    Applicant: Ikanos Communications, Inc.
    Inventors: Avadhani Shridhar, Kevin Fisher
  • Patent number: 8223859
    Abstract: A multi-tone modem with shared and discrete components forming a transmit path and a receive path configured to couple to a wired communication medium to communicate at least one multi-tone modulated communication channel thereon. The modem includes a multi-tone modulator component and a configurable frequency up converter component. The multi-tone modulator component is configured for multi-tone modulation and demodulation of a transmitted and received communication channel at a base band frequency range. The configurable frequency up converter component is coupled to the multi-tone modulator to selectably up convert the frequency range of the transmitted base band signal from the multi-tone modulator to that of a selected communication band and down convert received signals from the selected communication band to the base band for demodulation by the multi-tone modulator.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: July 17, 2012
    Assignee: Ikanos Communications, Inc.
    Inventors: Sam Heidari, Sivannarayana Nagireddi, Sigurd Schelstraete, Avadhani Shridhar
  • Patent number: 7881362
    Abstract: A multi-tone transceiver including: a channel controller and a plurality of components forming a transmit path and a receive path. The channel controller configured to determine bit-loading for each successive symbol or tone set based on a 1st noise margin target for a first subset of tones in each tone set dedicated to transport of a robust communications channel (RCC) and based on a 2nd noise margin target less than the 1st noise margin target for remaining tones in each tone set dedicated to a standard communications channel (SCC). The plurality of components forming the transmit and receive paths are responsive to the channel controller to select for data modulated on a given tone at least one of smaller constellations and higher gain scaling levels when the given tone corresponds to an RCC tone as compared to an SCC tone, whereby the first set of tones dedicated to the RCC exhibit greater immunity to noise variations than the remaining tones dedicated to the SCC.
    Type: Grant
    Filed: September 15, 2007
    Date of Patent: February 1, 2011
    Assignee: Ikanos Communications, Inc.
    Inventors: Avadhani Shridhar, Sam Heidari, Rouben Toumani, Ying Wu
  • Publication number: 20100002755
    Abstract: A multi-tone modem with shared and discrete components forming a transmit path and a receive path configured to couple to a wired communication medium to communicate at least one multi-tone modulated communication channel thereon. The modem includes a multi-tone modulator component and a configurable frequency up converter component. The multi-tone modulator component is configured for multi-tone modulation and demodulation of a transmitted and received communication channel at a base band frequency range. The configurable frequency up converter component is coupled to the multi-tone modulator to selectably up convert the frequency range of the transmitted base band signal from the multi-tone modulator to that of a selected communication band and down convert received signals from the selected communication band to the base band for demodulation by the multi-tone modulator.
    Type: Application
    Filed: June 25, 2009
    Publication date: January 7, 2010
    Applicant: IKANOS Communication, Inc.
    Inventors: Sam Heidari, Sivannarayana Nagireddi, Sigurd Schelstraete, Avadhani Shridhar