Patents by Inventor Avinash Muthya Narahari

Avinash Muthya Narahari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921641
    Abstract: A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using a compacted L2P having an erase-block granularity. For a host logical address, the compacted L2P table only has the physical address of the corresponding erase block, which provides a first part of the pertinent physical address. A controller of the data storage device calculates a second part of the pertinent physical address based on the superblock layout employed in the device and further based on the sequential write requirement to the superblocks. The controller then obtains the full physical address corresponding to the host logical address by combining the first and second parts. The erase-block granularity of the compacted L2P table enables the full L2P table of the device to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: March 5, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avinash Muthya Narahari, Rajthilak Dasarathan
  • Publication number: 20240070086
    Abstract: A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using a compacted L2P having an erase-block granularity. For a host logical address, the compacted L2P table only has the physical address of the corresponding erase block, which provides a first part of the pertinent physical address. A controller of the data storage device calculates a second part of the pertinent physical address based on the superblock layout employed in the device and further based on the sequential write requirement to the superblocks. The controller then obtains the full physical address corresponding to the host logical address by combining the first and second parts. The erase-block granularity of the compacted L2P table enables the full L2P table of the device to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Avinash Muthya Narahari, Rajthilak Dasarathan
  • Publication number: 20240069775
    Abstract: A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using first and second L2P tables of different respective granularities. In an example embodiment, the first L2P table has a finer (e.g., page-level) granularity and is used to perform L2P address translation for open zones. The second L2P table has a coarser (e.g., erase-block) granularity and is used to perform L2P address translation for finished zones. A controller of the data storage device performs granularity-changing transfers of L2P entries between the first and second L2P tables in response to a respective open zone becoming finished and in response to a new zone becoming open. The coarser granularity of the second L2P table enables the full L2P table to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Avinash Muthya Narahari, Rajthilak Dasarathan
  • Publication number: 20230418740
    Abstract: During a garbage collection process of a data storage device, superblocks may be filled with dummy data, which may decrease device performance. Embodiments described herein provide systems, methods, and computer readable media for varying a size of a superblock to reduce or eliminate dummy data in a data storage device including a plurality of superblocks. Each of the plurality of superblocks including a plurality of die blocks.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Inventors: Avinash Muthya Narahari, Sampath Kumar Raja Murthy, Aakar Deora
  • Patent number: 11853203
    Abstract: During a garbage collection process of a data storage device, superblocks may be filled with dummy data, which may decrease device performance. Embodiments described herein provide systems, methods, and computer readable media for varying a size of a superblock to reduce or eliminate dummy data in a data storage device including a plurality of superblocks. Each of the plurality of superblocks including a plurality of die blocks.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avinash Muthya Narahari, Sampath Kumar Raja Murthy, Aakar Deora