Abstract: An encoding method for enabling privacy-preserving aggregation of private data can include obtaining private data including a private value, determining a probabilistic status defining one of a first condition and a second condition, producing a multiset including a plurality of multiset values, and providing the multiset for aggregation with a plurality of additional multisets respectively generated for a plurality of additional private values. In response to the probabilistic status having the first condition, the plurality of multiset values is based at least in part on the private value, and in response to the probabilistic status having the second condition, the plurality of multiset values is a noise message. The noise message is produced based at least in part on a noise distribution that comprises a discretization of a continuous unimodal distribution supported on a range from zero to a number of multiset values included in the plurality of multiset values.

Abstract: Methods and systems for conditioning graph neural networks on affinity features. One of the methods includes obtaining graph data representing an input graph that comprises a set of nodes and a set of edges that each connect a respective pair of nodes, the graph data comprising respective node features for each of the nodes, edge features for each of the edges, and a respective weight for each of the edges; generating one or more affinity features, each affinity feature representing a property of one or more random walks through the graph guided by the respective weights for the edges; and processing the graph data using a graph neural network that is conditioned on the one or more affinity features to generate a task prediction for a machine learning task for the input graph.

Abstract: An encoding method for enabling privacy-preserving aggregation of private data can include obtaining private data including a private value, determining a probabilistic status defining one of a first condition and a second condition, producing a multiset including a plurality of multiset values, and providing the multiset for aggregation with a plurality of additional multisets respectively generated for a plurality of additional private values. In response to the probabilistic status having the first condition, the plurality of multiset values is based at least in part on the private value, and in response to the probabilistic status having the second condition, the plurality of multiset values is a noise message. The noise message is produced based at least in part on a noise distribution that comprises a discretization of a continuous unimodal distribution supported on a range from zero to a number of multiset values included in the plurality of multiset values.

Abstract: A time division multiplexing (TDM) method and apparatus for interfacing data from communication channels to a TDM bus. The TDM arrangement uses a shift register to control a tri-state buffer. The shift register regulates the tri-state buffer based on a data bit pattern loaded into the shift register. The data bit pattern corresponds to the status of the individual channels. Each channel is assigned a bit which indicates whether the channel is active or inactive. As the shift register shifts out data, the tri-state buffer allows data to flow onto the TDM bus when a bit indicating an active channel is present and insulates the TDM bus from the communication channels when a bit representing an inactive channel is present. A processor is used to control the interrelationship of the multiple communication channels and to generate the status bits to be loaded into the shift register. The processor fills the shift register through the use of a storage register.

Abstract: A time division multiplexing (TDM) method and apparatus for interfacing data channels with a TDM bus. The TDM interface uses a processor and a channel coordinator circuit to indicate which data channels are active, and to assign which TDM transmit channels and which TDM receive channels will correspond to the active data channels. The processor controls the flow of data by using a channel coordinator circuit which controls multiple shift registers. The multiple shift registers control the flow of data between the active channels and the TDM bus. Multiple storage registers are used to buffer the data flowing between the active channels and the shift registers.

Abstract: Techniques that may be used in communication systems include encoding a stream of data using concatenated BCH codes, communicating the encoded data over a transmission medium, and decoding the encoded data using the BCH codes. The overhead of the concatenated BCH codes may substantially match the overhead of the Reed-Solomon RS(255/239) code. Examples of pairs of concatenated BCH codes include [BCH(2040,1952), BCH(3904, 3832)] and [BCH(2040, 1941), BCH(3882, 3834)].

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

Abstract: A resource negotiation technique and apparatus which streamlines arbitration for access to a shared resource by centralizing arbitration for groups of shared resources such as control registers into an access register. An accessing agent first writes a request to an appropriate bit of a resource negotiation register (RNR), and then reads back a grant status. If the request for access to the shared resource is not successful in the first attempt, the requesting processor may continuously read the grant status until it is successful. Alternatively, the resource negotiation register may cause an interrupt in the requesting processor upon grant of access to the shared resource. A logic level indicating that access is denied generally indicates that another processor in the multi-processor system is currently granted access to the corresponding shared resource.

Abstract: The present invention provides a game port interface having a second processor interface in addition to an otherwise conventional first processor interface such that a second processor may directly poll the game port interface to detect movement of a joystick device while a first, host processor is in a low power mode. Thus, the second processor may identify movement in the joystick and initiate a wake up sequence in the first, host processor via a communication path between the two processor interfaces. The additional processor interface allows the second processor to poll the joystick without interfering with the normal operation of the joystick. The present invention provides the power savings benefits of maintaining a host processor in a low power mode while at the same allowing another processor which may or may not be in a reduced power mode to detect movement of the joystick and initiate a wake up sequence in the host processor in response thereto.

Abstract: An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.