Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

Abstract: A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.

Abstract: A method includes, in a memory including analog memory cells, storing first data in a group of the memory cells using a first type of storage command that writes respective analog values to the memory cells in the group. Second data is stored in the memory cells in the group, in addition to the first data, using a second type of storage command that modifies the respective analog values of the memory cells in the group. Upon detecting imminent interruption of electrical power to the memory during storage of the second data, a switch is made to perform an alternative storage operation that is faster than the second type of storage command and protects at least the first data from the interruption.

Abstract: A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption.

Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract: A storage device includes a non-volatile memory, a volatile memory and a controller. The volatile memory supports a normal mode and a self-refresh mode. The controller is configured to store data for a host in the non-volatile memory while using the volatile memory in the normal mode and, in response to receiving a power-down command from the host, to deactivate at least part of the storage device and to switch the volatile memory from the normal mode to the self-refresh mode.

Abstract: A method includes, in a host that stores data in a storage device, detecting an event that is indicative, statistically and not deterministically, of an imminent power shutdown in the host. A notification is sent to the storage device responsively to the detected event, so as to cause the storage device to initiate preparatory action for the imminent power shutdown.

Abstract: An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.

Abstract: A method includes storing data values in a group of memory cells that share a common isolating layer, by producing quantities of electrical charge representative of the data values at respective regions of the common isolating layer that are associated with the memory cells. A function, which relates a drift of the electrical charge in a given memory cell in the group to the data values stored in one or more other memory cells in the group, is estimated. The drift is compensated for using the estimated function.

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract: A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory.

Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

Abstract: A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption.

Abstract: A storage device includes a non-volatile memory, a volatile memory and a controller. The volatile memory supports a normal mode and a self-refresh mode. The controller is configured to store data for a host in the non-volatile memory while using the volatile memory in the normal mode and, in response to receiving a power-down command from the host, to deactivate at least part of the storage device and to switch the volatile memory from the normal mode to the self-refresh mode.

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract: A method includes, in a host that stores data in a storage device, instructing the storage device to operate in a power throttling mode that limits power consumption of the storage device to a selected power limit. Storage commands are generated in the host for execution by the storage device, wherein each of at least some of the storage commands is partitioned into multiple sub-commands having a maximal size that depends on the selected power limit. The sub-commands are sent for execution in the storage device.

Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.

Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.