Abstract: A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip: at least two processors, at least one rewritable memory which can be accessed by the two processors, at least one cache memory via which the first processor has access to the memory, at least one bridge via which the second processor has access to the memory.

Abstract: To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.

Abstract: A processor memory system which includes: a processor component provided with a processor and at least a first integrated RAM memory, at least one second, external memory which is coupled to the processor component via an interface, a programmable memory management component which is integrated in the processor component and checks, in the case of a data address requested by the processor, whether this data address is stored in the first RAM memory which serves as a fast memory and in which data from the external memory has been loaded in advance, wherein the memory management component indicates the RAM memory address at which the data associated with the memory address is stored if the data is present in the RAM memory, the data then being read from the RAM memory, and wherein, if the data address is not present in the RAM memory, the memory management component outputs an interrupt instruction to the processor which subsequently initiates the loading of the searched data address from the external memo

Abstract: The system and method for emulating a non-volatile memory, in particular a flash memory, embedded in an integrated circuit comprises an integrated circuit with the non-volatile memory, a processor, an interface, a control unit, which controls the embedded non-volatile memory and the interface, and a bus, which connects controllably the interface, the processor and the control unit. The system further comprises an external memory, connected to the interface, in which memory the emulation takes place. The control unit connects the external memory to the bus over the interface or the non-volatile memory to the bus. By using such a design, emulation of a slow embedded (internal) memory is simplified and modifications, e.g. software break points, patches and downloads, can be easily introduced, and processor accesses may be traced.

Abstract: A method of operating a storage system comprising a main memory and a cache memory structured in address-related lines, in which cache memory can be loaded with data from the main memory and be read out by a processor as required. During the processor's access to data of a certain address in the cache memory, at which address certain data from the main memory which has a corresponding address is stored, a test is made to determine whether sequential data s stored at the next address in the cache memory; and this sequential data, if unavailable, can be loaded from the main memory in the cache memory via a prefetch, the latter only taking place when the processor accesses a predefined line section lying in a line.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: A processor memory system which includes:

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.