Abstract: Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

Abstract: A receiver includes a common-gate low noise amplifier (LNA) configured to receive an RF input signal and produce an amplified RF signal. A down-converting passive mixer is configured to mix the amplified received RF input signal with a local oscillator signal generated by a local oscillator to generate a down-converted amplified signal. An amplifier is configured to amplify the down-converted signal and has an input impedances in on the order of ohms. Only a single LNA may be required to receive RF inputs in all frequency bands of a multi-band communication standard.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

Abstract: A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.

Abstract: At least some of the arithmetic operations of a filter or other digital process can be performed time sequentially, which may allow the arithmetic elements for the filter or other digital process to be used multiple times for multiple operations.

Abstract: A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.