Abstract: A hearing assistance device comprises a system in package (SIP) disposed within an enclosure. The SIP module comprises a first substrate having a first surface and an opposing second surface, the first substrate supporting a first subsystem configured to perform a first function. A second substrate has a first surface and an opposing second surface, the second substrate supporting a second subsystem configured to perform a second function. The second surfaces face each other and at least one of the second surfaces supports one or more components. An interconnect layer is separate from and bonded to and between the first and second substrates. The interconnect layer comprises a window and a region peripheral to the window. The window is sized to accommodate the one or more components and the peripheral region comprising electrical pathways for electrically connecting the first subsystem and the second subsystem.

Abstract: Disclosed herein, among other things, are systems and methods for improved circuit design for hearing assistance devices. One aspect of the present subject matter includes a hearing assistance device configured to compensate for hearing losses of a user. The hearing assistance device includes a substrate and an interposer embedded into the substrate to form a system in package module. According to various embodiments, the interposer includes one or more integrated circuits (ICs) on the interposer, the one or more ICs configured to provide electronics for the hearing assistance device.

Abstract: A hearing assistance device comprises a system in package (SIP) disposed within an enclosure. The SIP module comprises a first substrate having a first surface and an opposing second surface, the first substrate supporting a first subsystem configured to perform a first function. A second substrate has a first surface and an opposing second surface, the second substrate supporting a second subsystem configured to perform a second function. The second surfaces face each other and at least one of the second surfaces supports one or more components. An interconnect layer is separate from and bonded to and between the first and second substrates. The interconnect layer comprises a window and a region peripheral to the window. The window is sized to accommodate the one or more components and the peripheral region comprising electrical pathways for electrically connecting the first subsystem and the second subsystem.

Abstract: A hearing assistance device comprises a system in package (SIP) disposed within an enclosure. The SIP module comprises a first substrate having a first surface and an opposing second surface, the first substrate supporting a first subsystem configured to perform a first function. A second substrate has a first surface and an opposing second surface, the second substrate supporting a second subsystem configured to perform a second function. The second surfaces face each other and at least one of the second surfaces supports one or more components. An interconnect layer is separate from and bonded to and between the first and second substrates. The interconnect layer comprises a window and a region peripheral to the window. The window is sized to accommodate the one or more components and the peripheral region comprising electrical pathways for electrically connecting the first subsystem and the second subsystem.

Abstract: A hearing assistance device comprises a system in package (SIP) disposed within an enclosure. The SIP module comprises a first substrate having a first surface and an opposing second surface, the first substrate supporting a first subsystem configured to perform a first function. A second substrate has a first surface and an opposing second surface, the second substrate supporting a second subsystem configured to perform a second function. The second surfaces face each other and at least one of the second surfaces supports one or more components. An interconnect layer is separate from and bonded to and between the first and second substrates. The interconnect layer comprises a window and a region peripheral to the window. The window is sized to accommodate the one or more components and the peripheral region comprising electrical pathways for electrically connecting the first subsystem and the second subsystem.

Abstract: Disclosed herein, among other things, are systems and methods for improved circuit design for hearing assistance devices. One aspect of the present subject matter includes a hearing assistance device configured to compensate for hearing losses of a user. The hearing assistance device includes a substrate and an interposer embedded into the substrate to form a system in package module. According to various embodiments, the interposer includes one or more integrated circuits (ICs) on the interposer, the one or more ICs configured to provide electronics for the hearing assistance device.

Abstract: Disclosed herein, among other things, are systems and methods for improved circuit design for hearing assistance devices. One aspect of the present subject matter includes a hearing assistance device configured to compensate for hearing losses of a user. The hearing assistance device includes a flexible circuit substrate and an integrated circuit die embedded within the flexible circuit substrate. The integrated circuit die includes a digital signal processor (DSP) die, in an embodiment. In various embodiments, the DSP die includes a DSP configured to provide processing for the hearing assistance device.

Abstract: A method, system, and computer program product for a faster identification of available reference designators (ARDs) in a design automation system. An ARD utility detects a selection of one or more selected component types for placement on a circuit schematic. A list containing one or more unavailable reference designators (URDs) is sorted through to identify one or more ARDs from the list of URDs. A list of ARDs is then generated, from which a pre-determined portion of ARDs are reserved. The reserved list of ARDs is then outputted for selection by a user.

Abstract: A method, system, and computer program product for a faster identification of available reference designators (ARDs) in a design automation system. An ARD utility detects a selection of one or more selected component types for placement on a circuit schematic. A list containing one or more unavailable reference designators (URDs) is sorted through to identify one or more ARDs from the list of URDs. A list of ARDs is then generated, from which a pre-determined portion of ARDs are reserved. The reserved list of ARDs is then outputted for selection by a user.

Abstract: An apparatus and method for simulation and testing of electronic systems using a single model that has the composite behavioral information of multiple parts. The single model allows the designer to simulate using one model that captures the anticipated extremes (best case behavior to worst case behavior) across a collection of devices from different vendors.

Abstract: A via resistor structure and method are provided for implementing a resistor and for trimming a resistance value of the resistor. A resistive material selectively is deposited adjacent to a pad connecting to a via where a resistor is to be defined. A trimmed path is formed in the resistive material for selectively changing the resistance value of the resistor.

Abstract: An apparatus and method for simulation and testing of electronic systems using a single model that has the composite behavioral information of multiple parts. The single model allows the designer to simulate using one model that captures the anticipated extremes (best case behavior to worst case behavior) across a collection of devices from different vendors.

Abstract: An electronic assembly and system and method implementing the same are disclosed herein. The electronic assembly includes an IC carrier package having circuitry contained within a housing unit. The IC carrier package includes a connector interface for electrically coupling the IC carrier package circuitry to a printed circuit board. The connector interface is further characterized as having a graduated step surface contour with one or more electrical contacts disposed on at least two graduated step connector surfaces of the connector interface. The electronic assembly further includes a multilayer printed circuit board having a mounting site cavity for mounting the IC carrier package. The mounting site cavity includes having at least two seating surfaces offset in a graduated step manner for receivably seating the at least two graduated step connector surfaces of the IC carrier package connector interface.

Abstract: A high frequency connector utilizes flex strip signal/reference conductor pairs extending in channels formed in a dielectric connector body between terminations at connector ends. The flex strips are formed as signal and reference conductor traces separated by a flexible dielectric wherein the impedance can be influenced by the width of the signal and reference traces and the thickness and selected material of the dielectric separating the adjoining conductor traces. Design of the flex strip assemblies is used to vary the capacitance which enables the connector impedance to match the impedance of the circuits and/or cables connected to the connector and mitigate any discontinuities among the sequence of circuit paths. The close proximity of signal and reference traces within the pair and the separation of signal lines in the connector body reduces cross talk by minimizing mutual inductance between signal lines.

Abstract: A high frequency connector utilizes flex strip signal/reference conductor pairs extending in channels formed in a dielectric connector body between terminations at connector ends. The flex strips are formed as signal and reference conductor traces separated by a flexible dielectric wherein the impedance can be influenced by the width of the signal and reference traces and the thickness and selected material of the dielectric separating the adjoining conductor traces. Design of the flex strip assemblies is used to vary the capacitance which enables the connector impedance to match the impedance of the circuits and/or cables connected to the connector and mitigate any discontinuities among the sequence of circuit paths. The close proximity of signal and reference traces within the pair and the separation of signal lines in the connector body reduces cross talk by minimizing mutual inductance between signal lines.