Patents by Inventor Ayal Bar-David

Ayal Bar-David has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6813504
    Abstract: A method for dialing a telephone number indirectly, including obtaining an alphanumeric identifier that is assigned to a telephone subscriber and associating the identifier with a destination telephone number of the telephone subscriber to form a mapping therebetween. The method further includes storing the mapping in a lookup table, dialing the identifier using an originating telephone, using the identifier as a pointer to the lookup table so as to recover the destination telephone number from the stored mapping, and establishing a connection between the originating telephone and a destination telephone via the destination telephone number.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: November 2, 2004
    Assignee: QUALCOMM Incorporated
    Inventors: Uri Benchetrit, Ayal Bar-David, Yoram Rimoni
  • Publication number: 20030144013
    Abstract: A method for dialing a telephone number indirectly, including obtaining an alphanumeric identifier that is assigned to a telephone subscriber and associating the identifier with a destination telephone number of the telephone subscriber to form a mapping therebetween. The method further includes storing the mapping in a lookup table, dialing the identifier using an originating telephone, using the identifier as a pointer to the lookup table so as to recover the destination telephone number from the stored mapping, and establishing a connection between the originating telephone and a destination telephone via the destination telephone number.
    Type: Application
    Filed: January 25, 2002
    Publication date: July 31, 2003
    Inventors: Uri Benchetrit, Ayal Bar-David, Yoram Rimoni
  • Patent number: 6549051
    Abstract: A method for generating a variable delay of a signal, including: providing a clock indicating a sequence of sample times at regular intervals and receiving a sequence of input samples representing input values of the signal at respective sample times indicated by the clock. The method further includes determining the delay with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times. For each of the sample times, responsive to the respectively-determined delay, one or more of the input samples are processed so as to generate a corresponding output sample representing a delayed output value of the signal at the sample time.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: April 15, 2003
    Assignee: Qualcomm, Inc.
    Inventors: Maurizio Di Veroli, Ayal Bar-David
  • Patent number: 6094465
    Abstract: A method and apparatus for decoding a frame of multi-rate encoded digital data which contains redundant information provided to validate the decoding operation. A frame of data is received which contains information bits and cyclic redundancy check (CRC) bits. In accordance with the invention, the received frame is decoded and a check is conducted to determine whether the CRC bits correspond correctly for the decoded information bits. If the decoded frame passes the CRC test process, the decoded fame is provided to the user. However, if the decoded frame does not pass the CRC test, then at least one additional decoding process is performed on the received frame. In the first exemplary embodiment of the present invention, on a failure of the CRC check, the data is decoded using a trellis decoder and the data that yields the next most likely path through the trellis is selected.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 25, 2000
    Assignee: QUALCOMM Incorporated
    Inventors: Jeremy M. Stein, Ayal Bar-David
  • Patent number: 5202889
    Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.
    Type: Grant
    Filed: November 13, 1990
    Date of Patent: April 13, 1993
    Assignee: International Business Machines Corporation
    Inventors: Aharon Aharon, Ayal Bar-David, Raanan Gewirtzman, Emanuel Gofman, Moshe Leibowitz, Victor Shwartzburd