Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.

Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.

Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.

Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.

Abstract: A non-volatile logic device for energy-efficient logic state restoration is disclosed. The non-volatile logic device incorporates a volatile flip-flop and a non-volatile storage unit to achieve on-chip non-volatile storage. The non-volatile logic device further allows for a backup time to be determined on a per-chip basis, resulting in minimizing energy wastage and satisfying a given yield constraint.

Abstract: This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

Abstract: A non-volatile logic device for energy-efficient logic state restoration is disclosed. The non-volatile logic device incorporates a volatile flip-flop and a non-volatile storage unit to achieve on-chip non-volatile storage. The non-volatile logic device further allows for a backup time to be determined on a per-chip basis, resulting in minimizing energy wastage and satisfying a given yield constraint.

Abstract: A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

Abstract: This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

Abstract: A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.

Abstract: A method of modeling an integrated circuit includes: specifying a layout for the integrated circuit, wherein the layout includes a plurality of devices arranged in a plurality of layers and a plurality of connections between the layers; specifying locations for a source point and an observation point for the integrated circuit; determining a plurality of static images for the source point and the observation point; determining a plurality of discrete complex images for the source point and the observation point; determining a Green's-function value for the source point and the observation point by combining the static images and the discrete complex images; and saving at least some values based on the Green's-function value.

Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract: A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layout metrics from the one or more device variables and the one or more weights; and determining the IC design from the one or more device variables and the one or more net lengths. The IC design includes a schematic and a layout. The process can be repeated as needed according to performance criteria that may include circuit performance metrics and layout performance metrics.

Abstract: The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.