Patents by Inventor Azeez Bhavnagarwala
Azeez Bhavnagarwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120179412Abstract: Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, David J. Frank, Stephen V. Kosonocky
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Patent number: 8214169Abstract: Circuits and methods for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices, which enable circuit designers to accurately measure and characterize random variations in device characteristics (such as transistor threshold voltage) between neighboring devices resulting from random sources such as dopant fluctuations and line edge roughness, for purposes of integrated circuit design and analysis. In one aspect, a method for characterizing random variations in device mismatch (e.g., threshold voltage mismatch) between a pair of device (e.g., transistors) is performed by obtaining subthreshold DC voltage characteristic data for the device pair, and then determining a distribution in voltage threshold mismatch for the device pair directly from the corresponding subthreshold DC voltage characteristic data.Type: GrantFiled: August 18, 2003Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Azeez Bhavnagarwala, David J. Frank, Stephen V. Kosonocky
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Patent number: 7545671Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.Type: GrantFiled: May 30, 2008Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen V. Kosonocky, Sampath Purushothaman, Kenneth P. Rodbell
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Publication number: 20080225573Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.Type: ApplicationFiled: May 30, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen V. Kosonocky, Sampath Purushothaman, Kenneth P. Rodbell
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Patent number: 7397691Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.Type: GrantFiled: April 24, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen V. Kosonocky, Sampath Purushothaman, Kenneth P. Rodbell
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Publication number: 20070247896Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.Type: ApplicationFiled: April 24, 2006Publication date: October 25, 2007Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen Kosonocky, Sampath Purushothaman, Kenneth Rodbell
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High performance register file with bootstrapped storage supply and method of reading data therefrom
Patent number: 7180818Abstract: A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.Type: GrantFiled: November 22, 2004Date of Patent: February 20, 2007Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Azeez Bhavnagarwala -
Publication number: 20060215465Abstract: Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power supply and/or ground line voltages that are applied to the memory cells during different modes of memory operation to enable low voltage, high performance operation of the memory devices.Type: ApplicationFiled: March 25, 2005Publication date: September 28, 2006Inventors: Azeez Bhavnagarwala, Stephen Kosonocky
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High performance register file with bootstrapped storage supply and method of reading data thereform
Publication number: 20060109733Abstract: A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.Type: ApplicationFiled: November 22, 2004Publication date: May 25, 2006Inventors: Rajiv Joshi, Azeez Bhavnagarwala -
Publication number: 20060103023Abstract: A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen Kosonocky, Satyanarayana Nitta, Sampath Purushothaman
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Patent number: 6975532Abstract: A quasi-static random access memory cell exhibits increased READ mode operation stability by statically storing the cell logic value during idle periods and dynamically storing the cell logic value during READ mode operation.Type: GrantFiled: July 8, 2004Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: Stephen V. Kosonocky, Azeez Bhavnagarwala
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Patent number: 6920061Abstract: Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation.Type: GrantFiled: August 27, 2003Date of Patent: July 19, 2005Assignee: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Rajiv V. Joshi, Stephen V. Kosonocky
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Patent number: 6876595Abstract: Circuits and methods for controlling data access operations in memory devices such as SRAM (static random access memory) devices. The circuits and methods provide timing and control for memory access operations by propagating a control pulse along a decode path from which a sequence of control pulses are generated at points in the decode path to synchronize activation of wordlines and sense amplifiers and precharge/equalization of bit lines. Preferably, an address gated pulse schema is implemented to synchronize and restrict switching activity spatially and temporally to only regions of a memory array that are being accessed, and for limited periods of time just sufficient to generate signals for read or write operations. Advantageously, the circuits and methods enable SRAM cell delays to track CMOS gate delays more closely at low voltages and reduce switching power by restricting switching transitions only to the regions of memory that are accessed.Type: GrantFiled: June 5, 2003Date of Patent: April 5, 2005Assignee: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen V. Kosonocky
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Publication number: 20050047196Abstract: Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation.Type: ApplicationFiled: August 27, 2003Publication date: March 3, 2005Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Rajiv Joshi, Stephen Kosonocky
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Publication number: 20050043908Abstract: Circuits and methods for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices, which enable circuit designers to accurately measure and characterize random variations in device characteristics (such as transistor threshold voltage) between neighboring devices resulting from random sources such as dopant fluctuations and line edge roughness, for purposes of integrated circuit design and analysis. In one aspect, a method for characterizing random variations in device mismatch (e.g., threshold voltage mismatch) between a pair of device (e.g., transistors) is performed by obtaining subthreshold DC voltage characteristic data for the device pair, and then determining a distribution in voltage threshold mismatch for the device pair directly from the corresponding subthreshold DC voltage characteristic data.Type: ApplicationFiled: August 18, 2003Publication date: February 24, 2005Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, David Frank, Stephen Kosonocky
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Publication number: 20050018518Abstract: A memory device has a memory cell including a plurality of active devices, which can be switched on by an applied threshold voltage. A power line is coupled to at least one storage node by one of the active devices. One other of the active devices couples a virtual ground to the storage node. Potentials of the power line and the virtual ground cause the plurality of active devices to be selectively operated in near subthreshold and/or superthreshold regimes in accordance with a mode of operation.Type: ApplicationFiled: July 24, 2003Publication date: January 27, 2005Inventors: Azeez Bhavnagarwala, Stephen Kosonocky
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Publication number: 20040246812Abstract: Circuits and methods for controlling data access operations in memory devices such as SRAM (static random access memory) devices. The circuits and methods provide timing and control for memory access operations by propagating a control pulse along a decode path from which a sequence of control pulses are generated at points in the decode path to synchronize activation of wordlines and sense amplifiers and precharge/equalization of bit lines. Preferably, an address gated pulse schema is implemented to synchronize and restrict switching activity spatially and temporally to only regions of a memory array that are being accessed, and for limited periods of time just sufficient to generate signals for read or write operations. Advantageously, the circuits and methods enable SRAM cell delays to track CMOS gate delays more closely at low voltages and reduce switching power by restricting switching transitions only to the regions of memory that are accessed.Type: ApplicationFiled: June 5, 2003Publication date: December 9, 2004Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen V. Kosonocky