Patents by Inventor B. Allen Montijo

B. Allen Montijo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6052107
    Abstract: A method of displaying graticule window data on a computer screen is disclosed herein. The method generally commences as graticule window data (e.g., live signal traces, graticule lines, etc.) is written into a video random-access memory, and conventional display data is written into a display buffer. In response to synchronization signals, the conventional display data is read from the display buffer, and the graticule window data is converted into video data. Also in response to synchronization signals, and further in response to reading conventional display data matching a reference color, the video data is multiplexed with the conventional display data to create a video output. The video output is then used to illuminate the pixels of a computer screen. Computer apparatus for executing the method's steps is also disclosed.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: April 18, 2000
    Assignee: Hewlett-Packard Company
    Inventor: B. Allen Montijo
  • Patent number: 5900755
    Abstract: The phase of an acquisition clock for a digital oscilloscope is modulated by summing an offset voltage with the output of the phase detector of a phase lock loop. The offset voltage is generated by a digital-to-analog converter which is fed input values by a microprocessor running a number generator routine.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: May 4, 1999
    Assignee: Hewlett-Packard, Co.
    Inventors: Derek E. Toeppen, B. Allen Montijo, Reginald Kellum
  • Patent number: 5789954
    Abstract: The phase of an acquisition clock for a digital oscilloscope is modulated by summing an offset voltage with the output of the phase detector of a delay lock loop. The offset voltage is generated by a digital-to-analog converter which is fed input values by a microprocessor running a number generator routine.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: August 4, 1998
    Assignee: Hewlett-Packard Co.
    Inventors: Derek E. Toeppen, B. Allen Montijo, Reginald Kellum
  • Patent number: 5629947
    Abstract: The present invention comprises a runt fault detector which detects positive and negative runt faults based only upon the crossings of a high voltage threshold and a low voltage threshold. Specifically, the runt fault detector detects a positive runt fault when an input signal transitions from below to above the low voltage threshold and then back below the low voltage threshold without first transitioning from below to above the high voltage threshold. The runt fault detector also detects a negative runt fault when an input signal transitions from above to below the high voltage threshold and then back above the high voltage threshold without first transitioning from above to below the low voltage threshold. Simultaneous detection of both positive and negative runt faults may also be achieved by the present invention.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: May 13, 1997
    Assignee: Hewlett-Packard Company
    Inventors: Reginald Kellum, B. Allen Montijo
  • Patent number: 5180971
    Abstract: Circuits for increasing throughput in random repetitive signal acquisition systems that use triggers. The circuits allow the random repetitive signal acquisition systems to terminate an acquisition only when there is a high probability that usable samples have reached the systems. The circuits comprise logic elements for producing a qualifier signal having at least two input ports. A first delay element is coupled to a first input of the logic element for introducing a first delay in a sample signal, thereby producing a first delayed sample signal for setting the logic element and enabling the qualifier signal. A second delay element is coupled to a second input port of the logic element for introducing a second delay in the sample signal, thereby producing a second delayed sample signal for resetting the logic element and disabling the qualifier signal. The qualifying signal qualifies a trigger signal produced by trigger circuitry in the random repetitive signal acquisition system.
    Type: Grant
    Filed: June 17, 1991
    Date of Patent: January 19, 1993
    Assignee: Hewlett-Packard Company
    Inventor: B. Allen Montijo