Abstract: PCIe devices may be connected to a test system for development, quality assurance, manufacturing, design validation, qualification, certification, and other testing. PCIe bus or other unexpected errors can avoid direct capture by the test system. Inserting a PCIe analyzer can capture a trace of PCIe bus data around any specific trigger. Due to the high volume and speed of data crossing the data bus when testing multiple devices, finding a correct trigger for an analyzer trace capture is akin to finding a needle in a haystack. By configuring a specific trigger pattern that the test system can send across the PCIe bus without impacting any of the devices under test, the test system can trigger the analyzer at the precise time needed to capture a PCIe bus data trace around the error.

Abstract: The invention is a method of testing a storage network that includes a method of handling data at the port and bus level. The method includes emulating targets in computer memory, receiving data from initiators, and passing to computer memory only a portion of the data received. Bandwidth of internal memory and paths to memory are de-coupled from devices under test attached to ports, such that full bandwidth testing is possible at all test clients simultaneously. Data passed on a wire is returned or discarded at the port or bus level. The invention is useful for testing networks that have high bandwidths, and for testing large storage area networks.