Abstract: The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further con

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: A memory cell has first, second, third and fourth transistors forming first and second cross-coupled inverters. The inverters define first and inverted first storage nodes; the first connected to first reference and first supply voltages, second connected to second reference and second supply voltages. A fifth transistor connected between first storage node and first bit line; sixth transistor connected between inverted first node and second bit line; first word line connected to fifth transistor, controlling access of first bit line to first node; second word line connected to sixth transistor, controlling access of second bit line to inverted first node. Relative voltage levels of first word line and first reference voltages, or first supply and first reference voltages, or second word line and second reference voltages, or second supply and second reference voltages, or first and second reference voltages are configured so first/inverted node are read/written independently.

Abstract: A computer-implemented method for simulation of an integrated circuit for yield analysis includes: a) for plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of circuits; b) selecting at least one sample from each initial set randomly and combining into initial simulation set; c) running initial simulation of operation of circuit, applying initial simulation set, the operation having passing/failing criterion; d) if fails: storing samples of initial set into initial sampling distributions for each variable; e) repeating steps b)-d) until sufficient failures obtained; f) building importance sampling distribution based on each initial sampling distribution, the importance distribution having lower, center, upper portions; g) generating secondary simulation set by drawing samples from importance sampling distribution for each variable; h) simulating circuit by applying the secondary set; i) repeating steps g)-h); j) mapping resulting yie

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further con

Abstract: The present disclosure relates to a computer-implemented method for simulation of an integrated circuit for yield analysis of the integrated circuit, the method comprising the steps of: a) for a plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of the integrated circuits; b) selecting at least one sample from each initial sampling set randomly and combining the selected samples into an initial simulation set; c) running an initial simulation of an operation of the integrated circuit, applying the initial simulation set, wherein the operation has a criterion for passing and failing the operation; d) if the initial simulation fails: storing the samples of the initial simulation set into initial sampling distributions for each variable; e) repeating steps b)-d) until a sufficient number of failures have been obtained; f) building an importance sampling distribution based on each initial sampling distribution, the importance sampling di

Abstract: The present disclosure relates to a static random access memory and a memory cell for a static random access memory, the memory cell comprising: a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D?), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) a second supply voltage (VDD2); a fifth transistor (MS) connected between the first storage node (D) and a first bit line (BL1); a sixth transistor (M6) connected between the inverted first storage node (D) and a second bit line (BL2); a first word line (WL1) connected to the fifth transistor (MS), said first word line (WL1) controlling the access of the first bit

Abstract: The present disclosure relates to a computer-implemented method for implementing an integrated circuit comprising at least one random-access memory, the method comprising the steps of: defining a plurality of memory portions of the random-access memory and obtaining sizes of the memory portions; for each memory portion, generating a memory cell array block, the memory cell array blocks corresponding to the sizes of the memory portions, wherein instances of the memory cell array blocks are inferred into a description of the integrated circuit in a hardware description language; for each memory cell array block, generating timing models and physical models; synthesizing the description of the integrated circuit in the hardware description language, including peripheral logic for the memory cell array blocks, to a schematic representation of circuit elements; placing the circuit elements, including the memory cell array blocks and the peripheral logic, on the integrated circuit and routing wires between the circ

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: An underwear garment includes an extended rear top portion configured to resemble something other than underwear, such as human skin. The rear top portion may also be configured to resemble a clothing top, such as a shirt, blouse. In particular, the rear top portion may resemble a bottom section of shirt or blouse, such as with a lace pattern, so that the rear top portion appears as a shirt to an observer when exposed. The rear top portion may has a vertical length of ½ to 6 inches, and is noticeably higher than the top edge of a front portion of the underwear when worn. The front portion of the underwear includes a V-shaped top edge.