Abstract: Sensors for measuring angular acceleration about three mutually orthogonal axes, X, Y, Z or about the combination of these axes are disclosed. The sensor comprises a sensor subassembly. The sensor subassembly further comprises a base which is substantially parallel to the X-Y sensing plane; a proof mass disposed in the X-Y sensing plane and constrained to rotate substantially about the X, and/or Y, and/or Z, by at least one linkage and is responsive to angular accelerations about the X, and/or Y, and/or Z directions. Finally, the sensor includes at least one electrode at the base plate or perpendicular to the base plate and at least one transducer for each sensing direction of the sensor subassembly responsive to the angular acceleration. Multi-axis detection is enabled by adjusting a configuration of flexures and electrodes.

Abstract: Sensors for measuring angular acceleration about three mutually orthogonal axes, X, Y, Z or about the combination of these axes are disclosed. The sensor comprises a sensor subassembly. The sensor subassembly further comprises a base which is substantially parallel to the X-Y sensing plane; a proof mass disposed in the X-Y sensing plane and constrained to rotate substantially about the X, and/or Y, and/or Z, by at least one linkage and is responsive to angular accelerations about the X, and/or Y, and/or Z directions. Finally, the sensor includes at least one electrode at the base plate or perpendicular to the base plate and at least one transducer for each sensing direction of the sensor subassembly responsive to the angular acceleration. Multi-axis detection is enabled by adjusting a configuration of flexures and electrodes.

Abstract: A method of measuring the temperature of device under test includes the steps of injecting a first current into an on-chip diode wherein a die containing the on-chip diode is under test. A second current is injected into the on-chip diode. A junction temperature is calculated based on the first current and the second current.

Abstract: Optimizing a circuit by calculating at least one parameter of a circuit based on a first size of at least one sleep transistor, calculating at least one parameter of the logic circuit based on a second size of the at least one sleep transistor. This process may be repeated for different sizes of the at least one sleep transistor to determine an optimum size of the at least one sleep transistor to optimize at least one parameter of the logic circuit.

Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.

Abstract: An oscillator circuit is provided having an oscillating amplifier circuit connected to a resonator. The oscillator/amplifier and resonator are preferably fabricated on a single die using semiconductor fabrication tools. Included with the circuitry is a temperature sensor or transducer, an execution unit, non-volatile memory, a modulator, and frequency synthesizer, all of which are integrated together on the substrate, along with the piezoelectric crystal resonator. The frequency synthesizer can preferably include a phase-locked loop with a divider that is in a feedback loop of the phase-locked loop, in which a divide-by value is received from a modulator that achieves finer and higher resolution frequency selectivity from the voltage-controlled oscillator, also within the phase-locked loop, as an output from the crystal oscillator.

Abstract: Sensors for measuring angular acceleration about three mutually orthogonal axes, X, Y, Z or about the combination of these axes are disclosed. The sensor comprises a sensor subassembly. The sensor subassembly further comprises a base which is substantially parallel to the X-Y sensing plane; a proof mass disposed in the X-Y sensing plane and constrained to rotate substantially about the X, and/or Y, and/or Z, by at least one linkage and is responsive to angular accelerations about the X, and/or Y, and/or Z directions. Finally, the sensor includes at least one electrode at the base plate or perpendicular to the base plate and at least one transducer for each sensing direction of the sensor subassembly responsive to the angular acceleration. Multi-axis detection is enabled by adjusting a configuration of flexures and electrodes.

Abstract: A module operable to be mounted onto a surface of a board. The module includes a linear accelerometer to provide a first measurement output corresponding to a measurement of linear acceleration in at least one axis, and a first rotation sensor operable to provide a second measurement output corresponding to a measurement of rotation about at least one axis. The accelerometer and the first rotation sensor are formed on a first substrate. The module further includes an application specific integrated circuit (ASIC) to receive both the first measurement output from the linear accelerometer and the second measurement output from the first rotation sensor. The ASIC includes an analog-to-digital converter and is implemented on a second substrate. The first substrate is vertically bonded to the second substrate.

Abstract: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

Abstract: Circuits for regulating a voltage or current to a load(s).

Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.

Abstract: An oscillator circuit is provided having an oscillating amplifier circuit connected to a resonator. The oscillator/amplifier and resonator are preferably fabricated on a single die using semiconductor fabrication tools. Included with the circuitry is a temperature sensor or transducer, an execution unit, non-volatile memory, a modulator, and frequency synthesizer, all of which are integrated together on the substrate, along with the piezoelectric crystal resonator. The frequency synthesizer can preferably include a phase-locked loop with a divider that is in a feedback loop of the phase-locked loop, in which a divide-by value is received from a modulator that achieves finer and higher resolution frequency selectivity from the voltage-controlled oscillator, also within the phase-locked loop, as an output from the crystal oscillator.

Abstract: A mixed signal method and system for tuning a voltage controlled oscillator is described. The method includes dividing a frequency range of an oscillator circuit into a plurality of regions, digitally selecting and tuning one of the plurality of regions of the divided frequency range of the oscillator circuit, and further tuning the selected region of the frequency range of the oscillator circuit via one or more analog tuning elements.

Abstract: A single ended input circuit can receive an input signal and generate a correction voltage corresponding to a common mode voltage of the input signal. A comparison of the input signal can be adjusted in response to the correction voltage. In one arrangement, an input circuit (100) can include a compare section (102) with first input (104-0) and second input (104-1). The first input (104-0) can receive an input signal (IN). The second input (104-1) can receive a reference voltage generated by a common mode detect and hold (CMDH) section (106). A (CMDH) section (106) can include an integrator circuit (108), an analog-to-digital (A/D) converter circuit (110), a digital hold circuit (112), and a digital-to-analog (D/A) converter (114). A correction voltage generated by integrating the input signal can be applied as the generated reference voltage.

Abstract: A compensation circuit is disclosed. The compensation circuit includes a driver stage having an output, a differential output device including a base coupled to the output of the driver stage, and a feedback block coupled to a first emitter of the differential output device. The differential output device includes a second emitter to provide a differential output, and the feedback block generates a feedback signal to adjust the differential output. The first emitter comprises a replicating transistor, and is proximate to the second emitter of the differential output device. By keeping the replicating emitter near the differential output device, the variances of temperature and process over the semiconductor die do not affect the performance of the compensation circuit. The compensation circuit may also compensate for variations in common-emitter current gain.

Abstract: A latching circuit is provided that includes a latch, a storage element, and a selection circuit coupled between the latch and the storage element. The latch can receive true and complementary voltage values from, for example, a data bus and, if called upon, forward the latched value to the non-volatile storage element via the selection circuit. Control signals sent to the selection circuit allow the latched data to be written to or read from the storage element. Once programmed, the voltage values will remain in the latching circuit even after power is removed. If the latched data is not sent to the non-volatile storage element, the latching circuit essentially functions as a volatile latch, and the data will be lost if power is removed. The switching circuit thereby operates as a dual-purpose volatile and non-volatile latching circuit that can be embodied as an array of latching circuits that temporarily and/or permanently store true and complementary data signals.

Abstract: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

Abstract: A latching circuit is provided that includes a latch, a storage element, and a selection circuit coupled between the latch and the storage element. The latch can receive true and complementary voltage values from, for example, a data bus and, if called upon, forward the latched value to the non-volatile storage element via the selection circuit. Control signals sent to the selection circuit allow the latched data to be written to or read from the storage element. Once programmed, the voltage values will remain in the latching circuit even after power is removed. If the latched data is not sent to the non-volatile storage element, the latching circuit essentially functions as a volatile latch, and the data will be lost if power is removed. The switching circuit thereby operates as a dual-purpose volatile and non-volatile latching circuit that can be embodied as an array of latching circuits that temporarily and/or permanently store true and complementary data signals.

Abstract: A dynamic feedback bias circuit. A system utilizing the dynamic bias circuit includes a first bus agent and a second bus agent. The first bus agent generates a first signal having a first voltage swing. The second bus agent has a core which operates at a core operating voltage, the core operating voltage having an amplitude less than the first voltage swing. The second bus agent has an input device which receives the first signal from the first bus agent. The input device of the second bus agent is biased by the dynamic feedback bias circuit to provide a core signal with a voltage swing approximately equal to or less than the core operating voltage.

Abstract: A dynamic feedback bias circuit. A system utilizing the dynamic bias circuit includes a first bus agent and a second bus agent. The first bus agent generates a first signal having a first voltage swing. The second bus agent has a core which operates at a core operating voltage, the core operating voltage having an amplitude less than the first voltage swing. The second bus agent has an input device which receives the first signal from the first bus agent. The input device of the second bus agent is biased by the dynamic feedback bias circuit to provide a core signal with a voltage swing approximately equal to or less than the core operating voltage.